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Top-down ZnO nanowire field effect transistors for logic circuit applications

Top-down ZnO nanowire field effect transistors for logic circuit applications
Top-down ZnO nanowire field effect transistors for logic circuit applications
ZnO nanowire transistors have shown a great potential in gas and chemical sensing, high power IC, short wavelength photodetector and light emitting applications. This is due to ZnO excellent semiconducting properties of high bulk mobility, large bandgap of 3.4eV and optical transparency from visible to mid-infra red spectrum. There are two approaches to realise ZnO nanowires; bottom-up and top-down. Bottom-up fabricated ZnO nanowire transistors exhibit a high mobility > 1000 cm2/V.s and large output drain current but device electrical performance is difficult to reproduce due to size variation and material quality. Therefore, a top-down fabrication approach is an attractive option since nanowire properties and size can be controlled by process parameters. In this work, we propose a top-down fabrication approach to produce nanowires using a combined photolithography, atomic layer deposition and anisotropic plasma etching technology. ZnO nanowires were fabricated on 150mm diameter SiO2-Si wafer with a dimension of 40nm x 38nm. The nanowires are made into field-effect transistors with a channel length from 1.3um to 18.6µm to study channel scaling. Preliminary electrical measurements give field-effect mobility of 0.5 cm2/V.s to 3 cm2/V.s and Ion/Ioff of 2×106. We anticipate mobility improvement by 3 times through passivation of the nanowire surface thanks to reduction of donor and surface traps with potential for logic circuits in display applications.
M. Sultan, Suhana
cafa8fc3-e886-46cd-8093-160ddabd5a22
Ditshego, N.J.
3079ff03-acd7-41cd-a07e-ec4b037de260
Gunn, Robert
6492aa2c-1754-405e-ac62-0eedf0ed1757
Kalna, Karol
5bda7abf-e173-42ac-bc6a-8652a3898846
Ashburn, Peter
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Chong, Harold M.H.
795aa67f-29e5-480f-b1bc-9bd5c0d558e1
M. Sultan, Suhana
cafa8fc3-e886-46cd-8093-160ddabd5a22
Ditshego, N.J.
3079ff03-acd7-41cd-a07e-ec4b037de260
Gunn, Robert
6492aa2c-1754-405e-ac62-0eedf0ed1757
Kalna, Karol
5bda7abf-e173-42ac-bc6a-8652a3898846
Ashburn, Peter
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Chong, Harold M.H.
795aa67f-29e5-480f-b1bc-9bd5c0d558e1

M. Sultan, Suhana, Ditshego, N.J., Gunn, Robert, Kalna, Karol, Ashburn, Peter and Chong, Harold M.H. (2013) Top-down ZnO nanowire field effect transistors for logic circuit applications. European Material Research Society Fall Meeting 2013, Warsaw, Poland. 15 - 19 Sep 2013.

Record type: Conference or Workshop Item (Paper)

Abstract

ZnO nanowire transistors have shown a great potential in gas and chemical sensing, high power IC, short wavelength photodetector and light emitting applications. This is due to ZnO excellent semiconducting properties of high bulk mobility, large bandgap of 3.4eV and optical transparency from visible to mid-infra red spectrum. There are two approaches to realise ZnO nanowires; bottom-up and top-down. Bottom-up fabricated ZnO nanowire transistors exhibit a high mobility > 1000 cm2/V.s and large output drain current but device electrical performance is difficult to reproduce due to size variation and material quality. Therefore, a top-down fabrication approach is an attractive option since nanowire properties and size can be controlled by process parameters. In this work, we propose a top-down fabrication approach to produce nanowires using a combined photolithography, atomic layer deposition and anisotropic plasma etching technology. ZnO nanowires were fabricated on 150mm diameter SiO2-Si wafer with a dimension of 40nm x 38nm. The nanowires are made into field-effect transistors with a channel length from 1.3um to 18.6µm to study channel scaling. Preliminary electrical measurements give field-effect mobility of 0.5 cm2/V.s to 3 cm2/V.s and Ion/Ioff of 2×106. We anticipate mobility improvement by 3 times through passivation of the nanowire surface thanks to reduction of donor and surface traps with potential for logic circuits in display applications.

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More information

Published date: 16 September 2013
Venue - Dates: European Material Research Society Fall Meeting 2013, Warsaw, Poland, 2013-09-15 - 2013-09-19
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 355284
URI: http://eprints.soton.ac.uk/id/eprint/355284
PURE UUID: 0e42fe02-edc3-4cad-9e73-fdd675be5983
ORCID for Harold M.H. Chong: ORCID iD orcid.org/0000-0002-7110-5761

Catalogue record

Date deposited: 21 Aug 2013 14:13
Last modified: 11 Dec 2021 04:18

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Contributors

Author: Suhana M. Sultan
Author: N.J. Ditshego
Author: Robert Gunn
Author: Karol Kalna
Author: Peter Ashburn
Author: Harold M.H. Chong ORCID iD

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