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Integration of nanoscale memristor synapses in neuromorphic computing architectures

Integration of nanoscale memristor synapses in neuromorphic computing architectures
Integration of nanoscale memristor synapses in neuromorphic computing architectures
Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic computing approaches that can best exploit the properties of memristor and scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault tolerant by design.
memristor, neuromorphic
0957-4484
384010
Indiveri, Giacomo
2dcdb034-d331-48ad-80c3-23a7d69e1f4f
Linares-Barranco, Bernabe
164306aa-a690-4b0b-8b15-641279f0c7c4
Legenstein, Robert
4b546ba3-87f7-4228-aa97-b3379597c695
Deligeorgis, George
92bb5de0-70b1-446d-8506-566ef52de184
Prodromakis, Themistoklis
d58c9c10-9d25-4d22-b155-06c8437acfbf
Indiveri, Giacomo
2dcdb034-d331-48ad-80c3-23a7d69e1f4f
Linares-Barranco, Bernabe
164306aa-a690-4b0b-8b15-641279f0c7c4
Legenstein, Robert
4b546ba3-87f7-4228-aa97-b3379597c695
Deligeorgis, George
92bb5de0-70b1-446d-8506-566ef52de184
Prodromakis, Themistoklis
d58c9c10-9d25-4d22-b155-06c8437acfbf

Indiveri, Giacomo, Linares-Barranco, Bernabe, Legenstein, Robert, Deligeorgis, George and Prodromakis, Themistoklis (2013) Integration of nanoscale memristor synapses in neuromorphic computing architectures. Nanotechnology, 24 (38), 384010. (doi:10.1088/0957-4484/24/38/384010).

Record type: Article

Abstract

Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic computing approaches that can best exploit the properties of memristor and scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault tolerant by design.

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Published date: 2 September 2013
Keywords: memristor, neuromorphic
Organisations: Nanoelectronics and Nanotechnology

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Local EPrints ID: 356432
URI: https://eprints.soton.ac.uk/id/eprint/356432
ISSN: 0957-4484
PURE UUID: 6d7b752a-b953-41ae-9061-f9588daaf435

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Date deposited: 30 Sep 2013 14:12
Last modified: 18 Jul 2017 03:38

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Contributors

Author: Giacomo Indiveri
Author: Bernabe Linares-Barranco
Author: Robert Legenstein
Author: George Deligeorgis

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