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Modeling the effect of process variations on the delay and power of the digital circuit using fast simulators

Modeling the effect of process variations on the delay and power of the digital circuit using fast simulators
Modeling the effect of process variations on the delay and power of the digital circuit using fast simulators
Process variation has an increasingly dramatic effect on delay and power as process geometries shrink. Even if the amount of variation remains the same as in previous generations, it accounts for a greater percentage of process geometries as they get smaller. So an accurate prediction of path delay and power variability for real digital circuits in the current technologies is very important; however, its main drawback is the high runtime cost. In this paper, we present a new fast EDA tool which accelerates Monte Carlo based statistical static timing analysis (SSTA) for complex digital circuit. Parallel platforms like Message Passing Interface and POSIX® Threads and also the GPU-based CUDA platform suggests a natural fit for this analysis. So using these platforms, Monte Carlo based SSTA for complex digital circuits at 32, 45 and 65 nm has been performed. and of the pin-to-output delay and power distributions for all basic gates are extracted using a memory lookup from Hspice and then the results are extended to the complex digital circuit in a hierarchal manner on the parallel platforms. Results show that the GPU-based platform has the highest performance (speedup of 19�). The correctness of the Monte Carlo based SSTA implemented on a GPU has been verified by comparing its results with a CPU based implementation.
Monte Carlo methods, SPICE, digital circuits, electronic design automation, graphics processing units, logic gates, message passing, parallel architectures, statistical analysis, CUDA platform, EDA tool, GPU, HSPICE, Monte Carlo based statistical static timing analysis, POSIX threads, SSTA, basic gates, digital circuit, memory lookup, message passing interface, parallel platform, power distribution, process geometry, process variation, size 32 nm, size 45 nm, size 65 nm, Delays, Digital circuits, Graphics processing units, Instruction sets, Integrated circuit modeling, Logic gates, Graphic Processing Unit (GPU), Message Passing Interface (MPI), Monte Carlo, POSIX® Thread (Pthread), Statistical timing
1-6
Amirsoleimani, A.
95fbd4ff-4601-445c-9b60-29c5411a3d6f
Soleimani, H.
a028b019-db37-4de1-bad2-192fc8952b50
Ahmadi, A.
d66d59bd-f54c-4ad9-9f87-5d216d1fef1b
Bavandpour, M.
094a344e-6477-470d-84f3-b5364fe885db
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Amirsoleimani, A.
95fbd4ff-4601-445c-9b60-29c5411a3d6f
Soleimani, H.
a028b019-db37-4de1-bad2-192fc8952b50
Ahmadi, A.
d66d59bd-f54c-4ad9-9f87-5d216d1fef1b
Bavandpour, M.
094a344e-6477-470d-84f3-b5364fe885db
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Amirsoleimani, A., Soleimani, H., Ahmadi, A., Bavandpour, M. and Zwolinski, M. (2013) Modeling the effect of process variations on the delay and power of the digital circuit using fast simulators. 2013ICEE: 21st Iranian Conference on Electrical Engineering, Iran, Islamic Republic of. 14 - 16 May 2013. pp. 1-6 .

Record type: Conference or Workshop Item (Paper)

Abstract

Process variation has an increasingly dramatic effect on delay and power as process geometries shrink. Even if the amount of variation remains the same as in previous generations, it accounts for a greater percentage of process geometries as they get smaller. So an accurate prediction of path delay and power variability for real digital circuits in the current technologies is very important; however, its main drawback is the high runtime cost. In this paper, we present a new fast EDA tool which accelerates Monte Carlo based statistical static timing analysis (SSTA) for complex digital circuit. Parallel platforms like Message Passing Interface and POSIX® Threads and also the GPU-based CUDA platform suggests a natural fit for this analysis. So using these platforms, Monte Carlo based SSTA for complex digital circuits at 32, 45 and 65 nm has been performed. and of the pin-to-output delay and power distributions for all basic gates are extracted using a memory lookup from Hspice and then the results are extended to the complex digital circuit in a hierarchal manner on the parallel platforms. Results show that the GPU-based platform has the highest performance (speedup of 19�). The correctness of the Monte Carlo based SSTA implemented on a GPU has been verified by comparing its results with a CPU based implementation.

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More information

Published date: 2013
Venue - Dates: 2013ICEE: 21st Iranian Conference on Electrical Engineering, Iran, Islamic Republic of, 2013-05-14 - 2013-05-16
Keywords: Monte Carlo methods, SPICE, digital circuits, electronic design automation, graphics processing units, logic gates, message passing, parallel architectures, statistical analysis, CUDA platform, EDA tool, GPU, HSPICE, Monte Carlo based statistical static timing analysis, POSIX threads, SSTA, basic gates, digital circuit, memory lookup, message passing interface, parallel platform, power distribution, process geometry, process variation, size 32 nm, size 45 nm, size 65 nm, Delays, Digital circuits, Graphics processing units, Instruction sets, Integrated circuit modeling, Logic gates, Graphic Processing Unit (GPU), Message Passing Interface (MPI), Monte Carlo, POSIX® Thread (Pthread), Statistical timing
Organisations: EEE

Identifiers

Local EPrints ID: 361448
URI: https://eprints.soton.ac.uk/id/eprint/361448
PURE UUID: 1a540bbe-e612-439c-9334-1b61c8d54613
ORCID for M. Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 23 Jan 2014 16:15
Last modified: 06 Jun 2018 13:14

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