An improved instruction-level energy model for RISC microprocessors
An improved instruction-level energy model for RISC microprocessors
The power and energy consumed by a chip have become primary design constraints for embedded systems and are largely affected by software. However, there is a gap between software and hardware that makes it hard to predict which code consumes the least power before running it. Therefore, it is vital to discover which factors affect a program's energy consumption. In this paper we present an instruction-level power model for a single core, in-order RISC processor architecture. We do not analyze each instruction individually, but we study the average power and running time instead. We find the power in a processor is nearly constant, no matter what instructions are run, but the IO port power is related to the behavior of the program. Furthermore, we provide a model that takes the cache miss rate into consideration
349-352
Wang, Wei
85862755-49c9-4c7d-a1f4-d838d35cb7b7
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
2013
Wang, Wei
85862755-49c9-4c7d-a1f4-d838d35cb7b7
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Wang, Wei and Zwolinski, M.
(2013)
An improved instruction-level energy model for RISC microprocessors.
9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2013), Villach, Austria.
24 - 27 Jun 2013.
.
Record type:
Conference or Workshop Item
(Paper)
Abstract
The power and energy consumed by a chip have become primary design constraints for embedded systems and are largely affected by software. However, there is a gap between software and hardware that makes it hard to predict which code consumes the least power before running it. Therefore, it is vital to discover which factors affect a program's energy consumption. In this paper we present an instruction-level power model for a single core, in-order RISC processor architecture. We do not analyze each instruction individually, but we study the average power and running time instead. We find the power in a processor is nearly constant, no matter what instructions are run, but the IO port power is related to the behavior of the program. Furthermore, we provide a model that takes the cache miss rate into consideration
This record has no associated files available for download.
More information
Published date: 2013
Venue - Dates:
9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2013), Villach, Austria, 2013-06-24 - 2013-06-27
Organisations:
EEE
Identifiers
Local EPrints ID: 361452
URI: http://eprints.soton.ac.uk/id/eprint/361452
PURE UUID: e3dcb6af-51e3-4d8e-8755-16694d4838f0
Catalogue record
Date deposited: 24 Jan 2014 09:09
Last modified: 23 Jul 2022 01:33
Export record
Contributors
Author:
Wei Wang
Author:
M. Zwolinski
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.
View more statistics