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Monte Carlo Static Timing Analysis with statistical sampling

Monte Carlo Static Timing Analysis with statistical sampling
Monte Carlo Static Timing Analysis with statistical sampling
With aggressive scaling of CMOS technologies, MOSFET devices are subject to increasing amounts of independent local statistical variability. The causes of these statistical variations and their effects on device performance have been extensively studied, but their impact on circuit performance is still difficult to predict. This paper proposes a method for modeling the impact of random intra-die statistical variations on digital circuit timing. The method allows the variation modeled by large-scale statistical transistor simulations to be propagated up the design flow to the circuit level, by making use of commercial STA and standard cell characterization tools. By using statistical sampling techniques, we achieve close to the accuracy of full SPICE simulation, but with a computational effort similar to that of Statistical Static Timing Analysis, while removing some of the inaccurate assumptions of Statistical Static Timing Analysis
0026-2714
464-474
Merrett, Michael
bd23c4c9-5603-4946-8b8e-0f76c8184125
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Merrett, Michael
bd23c4c9-5603-4946-8b8e-0f76c8184125
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Merrett, Michael and Zwolinski, Mark (2014) Monte Carlo Static Timing Analysis with statistical sampling. Microelectronics Reliability, 54 (2), 464-474. (doi:10.1016/j.microrel.2013.10.016).

Record type: Article

Abstract

With aggressive scaling of CMOS technologies, MOSFET devices are subject to increasing amounts of independent local statistical variability. The causes of these statistical variations and their effects on device performance have been extensively studied, but their impact on circuit performance is still difficult to predict. This paper proposes a method for modeling the impact of random intra-die statistical variations on digital circuit timing. The method allows the variation modeled by large-scale statistical transistor simulations to be propagated up the design flow to the circuit level, by making use of commercial STA and standard cell characterization tools. By using statistical sampling techniques, we achieve close to the accuracy of full SPICE simulation, but with a computational effort similar to that of Statistical Static Timing Analysis, while removing some of the inaccurate assumptions of Statistical Static Timing Analysis

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More information

Published date: February 2014
Organisations: EEE

Identifiers

Local EPrints ID: 361453
URI: http://eprints.soton.ac.uk/id/eprint/361453
ISSN: 0026-2714
PURE UUID: f8590c0e-8815-46f1-831d-26a62a83939d
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 24 Jan 2014 09:15
Last modified: 19 Nov 2019 02:02

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