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An improved instruction-level power model for ARM11 microprocessor

An improved instruction-level power model for ARM11 microprocessor
An improved instruction-level power model for ARM11 microprocessor
The power and energy consumed by a chip has become the primary design constraint for embedded systems, which has led to a lot of work in hardware design techniques such as clock gating and power gating. The software can also affect the power usage of a chip, hence good software design can be used to reduce the power further. In this paper we present an instruction-level power model based on an ARM1176JZF-S processor to predict the power of software applications. Our model takes substantially less input data than existing high accuracy models and does not need to consider each instruction individually. We show that the power is related to both the distribution of instruction types and the operations per clock cycle (OPC) of the program. Our model does not need to consider the effect of two adjacent instructions, which saves a lot of calculation and measurements. Pipeline stall effects are also considered by OPC instead of cache miss, because there are a lot of other reasons that can cause the pipeline to stall. The model shows good performance with a maximum estimation error of -8.28\% and an average absolute estimation error is 4.88\% over six benchmarks. Finally, we prove that energy per operation (EPO) decreases with increasing operations per clock cycle, and we confirm the relationship empirically.
Wang, Wei
85862755-49c9-4c7d-a1f4-d838d35cb7b7
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Wang, Wei
85862755-49c9-4c7d-a1f4-d838d35cb7b7
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Wang, Wei and Zwolinski, Mark (2014) An improved instruction-level power model for ARM11 microprocessor. High Performance Energy Efficient Embedded Systems (HIP3ES), Berlin, Germany. 23 Jan 2013. 7 pp .

Record type: Conference or Workshop Item (Paper)

Abstract

The power and energy consumed by a chip has become the primary design constraint for embedded systems, which has led to a lot of work in hardware design techniques such as clock gating and power gating. The software can also affect the power usage of a chip, hence good software design can be used to reduce the power further. In this paper we present an instruction-level power model based on an ARM1176JZF-S processor to predict the power of software applications. Our model takes substantially less input data than existing high accuracy models and does not need to consider each instruction individually. We show that the power is related to both the distribution of instruction types and the operations per clock cycle (OPC) of the program. Our model does not need to consider the effect of two adjacent instructions, which saves a lot of calculation and measurements. Pipeline stall effects are also considered by OPC instead of cache miss, because there are a lot of other reasons that can cause the pipeline to stall. The model shows good performance with a maximum estimation error of -8.28\% and an average absolute estimation error is 4.88\% over six benchmarks. Finally, we prove that energy per operation (EPO) decreases with increasing operations per clock cycle, and we confirm the relationship empirically.

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More information

Published date: 23 January 2014
Venue - Dates: High Performance Energy Efficient Embedded Systems (HIP3ES), Berlin, Germany, 2013-01-23 - 2013-01-23
Organisations: EEE

Identifiers

Local EPrints ID: 361481
URI: http://eprints.soton.ac.uk/id/eprint/361481
PURE UUID: 8f60a3d0-3927-49f5-9848-67f074e75d87
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 24 Jan 2014 11:17
Last modified: 10 Apr 2020 00:24

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