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A Dynamic CDMA Network for Multicore Systems

A Dynamic CDMA Network for Multicore Systems
A Dynamic CDMA Network for Multicore Systems
Abstract- CDMA (code-division multiple-access) is a data transmission method based on the spreading code technology, where in multiple data streams share the same physical medium with no interference. A novel architecture for on-chip communication networks based on this approach is devised. The proposed design allows sharing coding resources among network’s users through the use of dynamic assignment of spreading codes. Data transmission latency is reduced by adopting a parallel structure for the coding/decoding circuitry. A 14-node CDMA network based on the proposed architecture is synthesized using 65nm ST technology library. Performance analysis reveals that the proposed approach achieves significantly lower data packet latency compared to both conventional CDMA and packet switched network-on-chip implementations. Large area and power savings compared to existing approaches are also obtained.
0026-2692
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
MA, Teng
13b031c4-e0e8-482b-8812-18f71cf9882e
Wei, Ximeng
bf0011ba-2b74-4453-bc32-977f134dce3d
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
MA, Teng
13b031c4-e0e8-482b-8812-18f71cf9882e
Wei, Ximeng
bf0011ba-2b74-4453-bc32-977f134dce3d

Halak, Basel, MA, Teng and Wei, Ximeng (2014) A Dynamic CDMA Network for Multicore Systems Microelectronics Journal

Record type: Article

Abstract

Abstract- CDMA (code-division multiple-access) is a data transmission method based on the spreading code technology, where in multiple data streams share the same physical medium with no interference. A novel architecture for on-chip communication networks based on this approach is devised. The proposed design allows sharing coding resources among network’s users through the use of dynamic assignment of spreading codes. Data transmission latency is reduced by adopting a parallel structure for the coding/decoding circuitry. A 14-node CDMA network based on the proposed architecture is synthesized using 65nm ST technology library. Performance analysis reveals that the proposed approach achieves significantly lower data packet latency compared to both conventional CDMA and packet switched network-on-chip implementations. Large area and power savings compared to existing approaches are also obtained.

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Accepted/In Press date: 29 July 2014
Organisations: EEE

Identifiers

Local EPrints ID: 361936
URI: http://eprints.soton.ac.uk/id/eprint/361936
ISSN: 0026-2692
PURE UUID: b938cb77-3772-4a4e-8b71-49c48122364b

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Date deposited: 06 Feb 2014 12:55
Last modified: 18 Jul 2017 02:57

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Contributors

Author: Basel Halak
Author: Teng MA
Author: Ximeng Wei

University divisions

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