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A Low-Cost Radiation Hardened Flip-Flop

A Low-Cost Radiation Hardened Flip-Flop
A Low-Cost Radiation Hardened Flip-Flop
Abstract—The aggressive scaling of semiconductor devices has
caused a significant increase in the soft error rate caused by
radiation hits. This has led to an increasing need for faulttolerant
techniques to maintain system reliability. Conventional
radiation hardening techniques, typically used in safety-critical
applications, are prohibitively expensive for non-safety-critical
electronics. This work proposes a novel flip-flop architecture
named SETTOFF which significantly improves circuit resilience
to radiation hits over previous techniques. In addition, compared
to other techniques such as a TMR latch, SETTOFF reduces
the area and performance overhead by up to 50% and 80%,
respectively; the power consumption is also reduced by up to
100%. In addition, a novel reliability metric called radiation induced failure rate is developed which can be a valuable tool to predict the impact of radiation hits and quantitatively compare the reliability of various radiation hardened techniques. Our analysis shows that the proposed technique can achieve zero SEU failure rate, and significantly reduce the SET failure rate.
Lin, Yang
4e10582f-310c-42c9-9bad-c6f8aa409a95
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Lin, Yang
4e10582f-310c-42c9-9bad-c6f8aa409a95
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33

Lin, Yang, Zwolinski, Mark and Halak, Basel (2014) A Low-Cost Radiation Hardened Flip-Flop At Design, Automation and Test in Europe (DATE).

Record type: Conference or Workshop Item (Paper)

Abstract

Abstract—The aggressive scaling of semiconductor devices has
caused a significant increase in the soft error rate caused by
radiation hits. This has led to an increasing need for faulttolerant
techniques to maintain system reliability. Conventional
radiation hardening techniques, typically used in safety-critical
applications, are prohibitively expensive for non-safety-critical
electronics. This work proposes a novel flip-flop architecture
named SETTOFF which significantly improves circuit resilience
to radiation hits over previous techniques. In addition, compared
to other techniques such as a TMR latch, SETTOFF reduces
the area and performance overhead by up to 50% and 80%,
respectively; the power consumption is also reduced by up to
100%. In addition, a novel reliability metric called radiation induced failure rate is developed which can be a valuable tool to predict the impact of radiation hits and quantitatively compare the reliability of various radiation hardened techniques. Our analysis shows that the proposed technique can achieve zero SEU failure rate, and significantly reduce the SET failure rate.

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More information

Published date: 2014
Venue - Dates: Design, Automation and Test in Europe (DATE), 2014-01-01
Organisations: EEE

Identifiers

Local EPrints ID: 361937
URI: http://eprints.soton.ac.uk/id/eprint/361937
PURE UUID: f40ad084-146c-46e3-b835-07d0d3a3059a
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 06 Feb 2014 12:56
Last modified: 18 Jul 2017 02:57

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Contributors

Author: Yang Lin
Author: Mark Zwolinski ORCID iD
Author: Basel Halak

University divisions

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