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An Energy-Efficient Radiation Hardened Register File Architecture for Reliable Microprocessors

An Energy-Efficient Radiation Hardened Register File Architecture for Reliable Microprocessors
An Energy-Efficient Radiation Hardened Register File Architecture for Reliable Microprocessors
Abstract—CMOS technology scaling has significantly increased
the susceptibility of microprocessors to radiation-induced
soft errors. The register file is one of the most vulnerable blocks
since it stores intermediate execution results and is frequently
accessed. Conventional error-tolerance techniques, such as ECC,
require large power and performance penalties to protect the
register file. This paper proposes a novel, radiation-hardened
register file architecture based on SETTOFF, a Soft Error and
Timing error Tolerant Flip-Flop. The proposed register file
significantly improves the error-tolerant capability over ECC,
since it can efficiently handle Multiple-Bit-Upsets (MBUs), and
can also tolerate both the SEUs occurred inside the register, and
the captured SETs originated in the preceding logic. Compared with ECC, the power overhead of the proposed register file is reduced by over 50%. In addition, a novel reliability metric called the radiation-induced failure rate is developed which can quantitatively evaluate the reliability of radiation hardened techniques. Our analysis shows that the proposed register file
can reduce the multiple-SEU failure rate to 0, and significantly reduce the multiple-SET failure rate.
Lin, Yang
4e10582f-310c-42c9-9bad-c6f8aa409a95
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Lin, Yang
4e10582f-310c-42c9-9bad-c6f8aa409a95
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33

Lin, Yang, Zwolinski, Mark and Halak, Basel (2014) An Energy-Efficient Radiation Hardened Register File Architecture for Reliable Microprocessors At Silicon Errors in Logic - System Effects (SELSE).

Record type: Conference or Workshop Item (Poster)

Abstract

Abstract—CMOS technology scaling has significantly increased
the susceptibility of microprocessors to radiation-induced
soft errors. The register file is one of the most vulnerable blocks
since it stores intermediate execution results and is frequently
accessed. Conventional error-tolerance techniques, such as ECC,
require large power and performance penalties to protect the
register file. This paper proposes a novel, radiation-hardened
register file architecture based on SETTOFF, a Soft Error and
Timing error Tolerant Flip-Flop. The proposed register file
significantly improves the error-tolerant capability over ECC,
since it can efficiently handle Multiple-Bit-Upsets (MBUs), and
can also tolerate both the SEUs occurred inside the register, and
the captured SETs originated in the preceding logic. Compared with ECC, the power overhead of the proposed register file is reduced by over 50%. In addition, a novel reliability metric called the radiation-induced failure rate is developed which can quantitatively evaluate the reliability of radiation hardened techniques. Our analysis shows that the proposed register file
can reduce the multiple-SEU failure rate to 0, and significantly reduce the multiple-SET failure rate.

Full text not available from this repository.

More information

Published date: 2014
Venue - Dates: Silicon Errors in Logic - System Effects (SELSE), 2014-01-01
Organisations: EEE

Identifiers

Local EPrints ID: 361943
URI: http://eprints.soton.ac.uk/id/eprint/361943
PURE UUID: 64667ae3-92ae-4be7-a4b3-5ef3f3b4a6ff
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 06 Feb 2014 12:56
Last modified: 18 Jul 2017 02:57

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Contributors

Author: Yang Lin
Author: Mark Zwolinski ORCID iD
Author: Basel Halak

University divisions

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