Design and validation of online fault tolerance architecture for TSV-based 3D-IC

Abstract

This technical report presents the design, validation and evaluation of an efficient online fault tolerance technique for fault detection and recovery in presence of three TSV defects: voids, delamination between TSV and landing pad, and TSV short-to-substrate. The technique employs transition delay test for TSV fault detection. Fault recovery is carried out by employing redundant TSVs and rerouting input/output signals to fault-free TSVs. This technique is efficient because it requires small (2 x number of TSVs per group) number of clock cycles for fault detection and recovery. Using 65-nm technology, simulations are carried out using HSPICE and ModelSim to validate fault detection and recovery. Synthesized RTL model of this technique is used to evaluate the area overhead. It is shown that regular and redundant TSVs can be divided into groups to minimize area overhead without affecting fault tolerance capability of the technique.

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