Investigating behavioural synthesis into bespoke instruction set processors

Abstract

We propose a new approach to the behavioural synthesis of digital systems for which a synthesis tool has been implemented.

Traditionally, behavioural synthesis tools convert the behaviour of a system into a RTL description, modelling a data-path and a controller. Instead, in the proposed approach, a behavioural description is translated into a RTL description that models a set of Bespoke Instruction Set Processors (BISPs). A BISP is a stripped-down microprocessor, which is composed of the minimal computational resources necessary to implement the part in the behavioural description from which it is derived. We refer to a BISP as a nano-processor throughout the thesis. This thesis looks at previous research on behavioural synthesis, describes the new approach and outlines the results of its evaluation and comparison to an existing behavioural synthesis tool. Results show that the new approach is less efficient than the existing technique when applied to small systems. However, the inability to support some VHDL constructs was the main obstacle against a full evaluation of the new approach.

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