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An energy efficient radiation hardened register file architecture

Lin, Yang, Zwolinski, Mark and Halak, Basel (2014) An energy efficient radiation hardened register file architecture At Designing with Uncertainty - Opportunities & Challenges Workshop, United Kingdom. 17 - 19 Mar 2014. 3 pp.

Record type: Conference or Workshop Item (Paper)


CMOS technology scaling has significantly increased the susceptibility of microprocessors to radiation-induced soft errors. The register file is one of the most vulnerable blocks since it stores intermediate execution results and is frequently accessed. Conventional error-tolerance techniques, such as ECC, require large power and performance penalties to protect the register file. This paper proposes a novel, radiation-hardened register file architecture based on SETTOFF, a Soft Error and Timing error Tolerant Flip-Flop. The proposed register file significantly improves the error-tolerant capability over ECC, since it can efficiently handle Multiple-Bit-Upsets (MBUs), and can also tolerate both the SEUs occurred inside the register, and the captured SETs originated in the preceding logic. Compared with ECC,the power overhead of the proposed register file is reduced by over 50%. In addition, a novel reliability metric called the radiation-induced failure rate is developed which can quantitatively evaluate the reliability of radiation hardened techniques. Our analysis shows that the proposed register file can reduce the multiple-SEU failure rate to 0, and significantly reduce the multiple-SET failure rate.

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Published date: March 2014
Venue - Dates: Designing with Uncertainty - Opportunities & Challenges Workshop, United Kingdom, 2014-03-17 - 2014-03-19
Organisations: EEE


Local EPrints ID: 363799
PURE UUID: 86f938af-ed48-4800-960f-2ae6759c7c53
ORCID for Mark Zwolinski: ORCID iD

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Date deposited: 03 Apr 2014 14:37
Last modified: 18 Jul 2017 02:35

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Author: Yang Lin
Author: Mark Zwolinski ORCID iD
Author: Basel Halak

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