High throughput CDMA communication architecture for many cores systems
High throughput CDMA communication architecture for many cores systems
CDMA (code-division multiple-access) is a data transmission method based on the spreading code technology, where in multiple data streams share the same physical medium with no interference. A novel architecture for on-chip communication networks based on this approach is devised. The proposed design allows sharing coding resources among network’s users through the use of dynamic assignment of spreading codes. Data transmission latency is reduced by adopting a parallel structure for the coding/decoding circuitry. A 14-node CDMA network based on the proposed architecture is synthesised using 65nm ST technology library. Performance analysis reveals that the proposed approach achieves significantly lower data packet latency compared to both conventional CDMA and packet switched network-on-chip implementations . Large area and power savings compared to existing approaches are also obtained.
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Ma, Teng
13b031c4-e0e8-482b-8812-18f71cf9882e
Ximeng, Wei
c9c3f66d-3402-48c8-9122-0aa4cb77a430
March 2014
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Ma, Teng
13b031c4-e0e8-482b-8812-18f71cf9882e
Ximeng, Wei
c9c3f66d-3402-48c8-9122-0aa4cb77a430
Halak, Basel, Ma, Teng and Ximeng, Wei
(2014)
High throughput CDMA communication architecture for many cores systems.
Designing with Uncertainty - Opportunities & Challenges Workshop, York, United Kingdom.
17 - 19 Mar 2014.
2 pp
.
Record type:
Conference or Workshop Item
(Paper)
Abstract
CDMA (code-division multiple-access) is a data transmission method based on the spreading code technology, where in multiple data streams share the same physical medium with no interference. A novel architecture for on-chip communication networks based on this approach is devised. The proposed design allows sharing coding resources among network’s users through the use of dynamic assignment of spreading codes. Data transmission latency is reduced by adopting a parallel structure for the coding/decoding circuitry. A 14-node CDMA network based on the proposed architecture is synthesised using 65nm ST technology library. Performance analysis reveals that the proposed approach achieves significantly lower data packet latency compared to both conventional CDMA and packet switched network-on-chip implementations . Large area and power savings compared to existing approaches are also obtained.
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Published date: March 2014
Venue - Dates:
Designing with Uncertainty - Opportunities & Challenges Workshop, York, United Kingdom, 2014-03-17 - 2014-03-19
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 363802
URI: http://eprints.soton.ac.uk/id/eprint/363802
PURE UUID: 5303a7ce-b6a2-4401-8654-61b7d3bf16f9
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Date deposited: 03 Apr 2014 14:52
Last modified: 11 Dec 2021 04:33
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Contributors
Author:
Basel Halak
Author:
Teng Ma
Author:
Wei Ximeng
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