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An architecture for measuring network performance in multi-core multi-cluster architecture (MCMCA)

An architecture for measuring network performance in multi-core multi-cluster architecture (MCMCA)
An architecture for measuring network performance in multi-core multi-cluster architecture (MCMCA)
The aim of this research is to design a new architecture for large-scale clusters to improve the communication within the interconnection network to gain higher performance. The new architecture will be based on clusters built using workstations containing multi cored processors in a multi-cluster architecture in the presence of uniform traffic. Multi-core technology is proposed to achieve higher performance without driving up power consumption and heat, which is the main concern in a single-core processor. The architecture will avoid congestion and deadlocks in the network to guarantee faster message transmission. The architecture performance will be validated through simulation, experimental and measurements under various working conditions.
57-61
Hamid, Norhazlina
22e1e955-20ef-4d80-92e3-1d2e8813f334
Walters, Robert J.
7b8732fb-3083-4f4d-844e-85a29daaa2c1
Wills, Gary B.
3a594558-6921-4e82-8098-38cd8d4e8aa0
Hamid, Norhazlina
22e1e955-20ef-4d80-92e3-1d2e8813f334
Walters, Robert J.
7b8732fb-3083-4f4d-844e-85a29daaa2c1
Wills, Gary B.
3a594558-6921-4e82-8098-38cd8d4e8aa0

Hamid, Norhazlina, Walters, Robert J. and Wills, Gary B. (2015) An architecture for measuring network performance in multi-core multi-cluster architecture (MCMCA). International Journal of Computer Theory and Engineering, 7 (1), 57-61.

Record type: Article

Abstract

The aim of this research is to design a new architecture for large-scale clusters to improve the communication within the interconnection network to gain higher performance. The new architecture will be based on clusters built using workstations containing multi cored processors in a multi-cluster architecture in the presence of uniform traffic. Multi-core technology is proposed to achieve higher performance without driving up power consumption and heat, which is the main concern in a single-core processor. The architecture will avoid congestion and deadlocks in the network to guarantee faster message transmission. The architecture performance will be validated through simulation, experimental and measurements under various working conditions.

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EACCI2014 NORHAZLINA HAMID_CAMERA_READY.pdf - Other
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More information

Published date: February 2015
Venue - Dates: 2014 Euro-Asia Conference on Computational Intelligence and Communication Networks (EACCI 2014), Antalya, Turkey, 2014-04-20 - 2014-04-22
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 364521
URI: http://eprints.soton.ac.uk/id/eprint/364521
PURE UUID: 21cfc29a-c924-4274-8a1d-d64fe58aa214
ORCID for Gary B. Wills: ORCID iD orcid.org/0000-0001-5771-4088

Catalogue record

Date deposited: 07 May 2014 13:34
Last modified: 18 Feb 2021 16:46

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Contributors

Author: Norhazlina Hamid
Author: Robert J. Walters
Author: Gary B. Wills ORCID iD

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