Efficient simulation and modelling of non-rectangular NoC topologies

Abstract

With increasing chip complexity, Networks-on-
Chips (NoCs) are becoming a central platform for future onchip
communications. Many regular NoC architectures have
been proposed to eliminate the communication bottlenecks of
traditional bus-based networks. Non-rectangular and irregular
architectures have also been proposed to increase performance.
However, the complexity of designing custom non-rectangular
networks leads to a rapid increase in design and verification times.
To alleviate the conflict between performance and efficiency, this
paper proposes a novel method that efficiently constructs virtual
non-rectangular topologies on a mesh network by using timeregulated
models to emulate irregular patterns. Data routings
on virtual hexagonal and two irregular geometries validate the
proposed method. An MPEG-4 decoder is used to exemplify the
proposed method for media applications. Results analysis shows
the virtual topologies emulated by the proposed method can
provide precise timing and energy performance.

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Identifiers

ORCID for Mark Zwolinski: orcid.org/0000-0002-2230-625X

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