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CARM: congestion adaptive routing method for on chip networks

CARM: congestion adaptive routing method for on chip networks
CARM: congestion adaptive routing method for on chip networks
Network-on-Chip (NoC) has emerged as a long-term and efficient on-chip communication solution for MC-SoC and CMP micro-architectures to overcome bottleneck of traditional bus-based interconnects. Performance of NoC is highly dependent on routing algorithm we choose. In this paper, we present a highly adaptive and deadlock free routing algorithm for 2D mesh topology to mitigate congestion. Proposed algorithm provides a high degree of adaptiveness by allowing cycles in channel dependency graph and using one additional virtual channel along the Y dimension only. It uses all available minimal/non-minimal paths between source and destination nodes. A packet is routed along the non-minimal path only when minimal paths get congested at the neighboring nodes. Results show that proposed congestion-aware routing algorithm improves network performance by routing packets through non-congested areas
graph theory, integrated circuit interconnections, network-on-chip, telecommunication network routing, 2D mesh topology, CARM, CMP microarchitectures, MCSoC, NoC, bus-based interconnects, channel dependency graph, chip multiprocessors, congestion adaptive routing method, congestion mitigation, congestion-aware routing algorithm, deadlock free routing algorithm, destination nodes, efficient on-chip communication solution, minimal path, neighboring nodes, nonminimal paths, on chip networks, routing packets, source nodes, virtual channel, Adaptation models, Algorithm design and analysis, Power demand, Routing, System recovery, System-on-chip, Throughput, Networks on Chip, congestion, deadlock freedom, non-minimal paths, routing
240-245
Kumar, M.
a1762b22-859d-4c14-919f-5cdabc7abfbf
Laxmi, V.
8ba515fc-a1f3-4685-8fac-3519ae9de905
Gaur, M.S.
d4a63afd-c0a0-479e-9a17-e93d99630bd3
Ko, S.-B.
194581e6-eff1-4ea0-a6b7-cefbea1f0749
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Kumar, M.
a1762b22-859d-4c14-919f-5cdabc7abfbf
Laxmi, V.
8ba515fc-a1f3-4685-8fac-3519ae9de905
Gaur, M.S.
d4a63afd-c0a0-479e-9a17-e93d99630bd3
Ko, S.-B.
194581e6-eff1-4ea0-a6b7-cefbea1f0749
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Kumar, M., Laxmi, V., Gaur, M.S., Ko, S.-B. and Zwolinski, M. (2014) CARM: congestion adaptive routing method for on chip networks. 27th International Conference on Design and 13th International Conference on Embedded Systems, 2014, Mumbai, India. 05 - 09 Jan 2014. pp. 240-245 . (doi:10.1109/VLSID.2014.48).

Record type: Conference or Workshop Item (Other)

Abstract

Network-on-Chip (NoC) has emerged as a long-term and efficient on-chip communication solution for MC-SoC and CMP micro-architectures to overcome bottleneck of traditional bus-based interconnects. Performance of NoC is highly dependent on routing algorithm we choose. In this paper, we present a highly adaptive and deadlock free routing algorithm for 2D mesh topology to mitigate congestion. Proposed algorithm provides a high degree of adaptiveness by allowing cycles in channel dependency graph and using one additional virtual channel along the Y dimension only. It uses all available minimal/non-minimal paths between source and destination nodes. A packet is routed along the non-minimal path only when minimal paths get congested at the neighboring nodes. Results show that proposed congestion-aware routing algorithm improves network performance by routing packets through non-congested areas

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More information

Published date: January 2014
Venue - Dates: 27th International Conference on Design and 13th International Conference on Embedded Systems, 2014, Mumbai, India, 2014-01-05 - 2014-01-09
Keywords: graph theory, integrated circuit interconnections, network-on-chip, telecommunication network routing, 2D mesh topology, CARM, CMP microarchitectures, MCSoC, NoC, bus-based interconnects, channel dependency graph, chip multiprocessors, congestion adaptive routing method, congestion mitigation, congestion-aware routing algorithm, deadlock free routing algorithm, destination nodes, efficient on-chip communication solution, minimal path, neighboring nodes, nonminimal paths, on chip networks, routing packets, source nodes, virtual channel, Adaptation models, Algorithm design and analysis, Power demand, Routing, System recovery, System-on-chip, Throughput, Networks on Chip, congestion, deadlock freedom, non-minimal paths, routing
Organisations: EEE

Identifiers

Local EPrints ID: 364711
URI: http://eprints.soton.ac.uk/id/eprint/364711
PURE UUID: 73aca89d-da31-4cd1-8a3d-a6c4f62ff3dc
ORCID for M. Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

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Date deposited: 09 May 2014 14:07
Last modified: 17 Dec 2019 02:03

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