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Parallel sparse matrix solution for circuit simulation on FPGAs

Parallel sparse matrix solution for circuit simulation on FPGAs
Parallel sparse matrix solution for circuit simulation on FPGAs
SPICE is the de facto standard for circuit simulation. However, accurate SPICE simulations of today’s sub-micron circuits can often take days or weeks on conventional processors. A SPICE simulation is an iterative process that consists of two phases per iteration: model evaluation followed by a matrix solution. The model evaluation phase has been found to be easily parallelizable, unlike the subsequent phase, which involves the solution of highly sparse and asymmetric matrices. In this paper, we present an FPGA implementation of a sparse matrix solver, geared towards matrices that arise in SPICE circuit simulations. Our approach combines static pivoting with symbolic analysis to compute an accurate task flow-graph which efficiently exploits parallelism at multiple granularities and sustains high floating-point data rates. We also present a quantitative comparison between the performance of our hardware prototype and state-of-the-art software packages running on a general-purpose PC.We report average speed-ups of 9.65, 11.83, and 17.21 against UMFPACK, KLU, and Kundert Sparse matrix packages, respectively
Algorithm design and analysis, Equations, Field programmable gate arrays, Matrix decomposition, Parallel processing, SPICE, Sparse matrices
1090-1103
Nechma, T.
deba5c5a-16d2-47a8-a8a9-a16f046cca0c
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Nechma, T.
deba5c5a-16d2-47a8-a8a9-a16f046cca0c
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Nechma, T. and Zwolinski, M. (2014) Parallel sparse matrix solution for circuit simulation on FPGAs. IEEE Transactions on Computers, 64 (4), 1090-1103, [6747987]. (doi:10.1109/TC.2014.2308202).

Record type: Article

Abstract

SPICE is the de facto standard for circuit simulation. However, accurate SPICE simulations of today’s sub-micron circuits can often take days or weeks on conventional processors. A SPICE simulation is an iterative process that consists of two phases per iteration: model evaluation followed by a matrix solution. The model evaluation phase has been found to be easily parallelizable, unlike the subsequent phase, which involves the solution of highly sparse and asymmetric matrices. In this paper, we present an FPGA implementation of a sparse matrix solver, geared towards matrices that arise in SPICE circuit simulations. Our approach combines static pivoting with symbolic analysis to compute an accurate task flow-graph which efficiently exploits parallelism at multiple granularities and sustains high floating-point data rates. We also present a quantitative comparison between the performance of our hardware prototype and state-of-the-art software packages running on a general-purpose PC.We report average speed-ups of 9.65, 11.83, and 17.21 against UMFPACK, KLU, and Kundert Sparse matrix packages, respectively

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Accepted/In Press date: 29 December 2013
e-pub ahead of print date: 24 February 2014
Published date: 24 February 2014
Keywords: Algorithm design and analysis, Equations, Field programmable gate arrays, Matrix decomposition, Parallel processing, SPICE, Sparse matrices
Organisations: EEE

Identifiers

Local EPrints ID: 364713
URI: http://eprints.soton.ac.uk/id/eprint/364713
PURE UUID: 456882d4-d1dd-48bf-b95a-f0cfb3856071
ORCID for M. Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 09 May 2014 14:23
Last modified: 07 Apr 2020 00:24

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