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A cost-efficient self-checking register architecture for radiation hardened designs

A cost-efficient self-checking register architecture for radiation hardened designs
A cost-efficient self-checking register architecture for radiation hardened designs
The rapid development of CMOS technology has significantly increased the susceptibility of electronic systems to radiation-induced soft errors. Conventional error-tolerant techniques typically use redundancies to mitigate soft errors and increase system immunity. However they do not have selfchecking capabilities, and therefore are still vulnerable to the errors in the redundant circuitry added for error-tolerance. This paper proposes a novel self-checking soft error-tolerant register based on SETTOFF, a Soft Error and Timing error Tolerant Flip-Flop. The register significantly improves the error-tolerant capability over previous techniques since it has a self-checking capability, which allows the register to tolerate both the errors in the original flip-flops and the redundant circuitry. In addition, the register can also tolerate both soft errors (SETs and SEUs) and timing errors. Compared with other previous techniques such as TMR, the proposed register reduces the power consumption overhead by 81%, and the delay overhead by 54% in 65nm technology; The area overhead is also reduced by 25%
Lin, Yang
d4e84e6a-39d9-4608-af5b-6d5d0fedb38f
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Lin, Yang
d4e84e6a-39d9-4608-af5b-6d5d0fedb38f
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Lin, Yang and Zwolinski, Mark (2014) A cost-efficient self-checking register architecture for radiation hardened designs. International Symposium on Circuits and Systems, Australia. 01 - 05 Jun 2014.

Record type: Conference or Workshop Item (Paper)

Abstract

The rapid development of CMOS technology has significantly increased the susceptibility of electronic systems to radiation-induced soft errors. Conventional error-tolerant techniques typically use redundancies to mitigate soft errors and increase system immunity. However they do not have selfchecking capabilities, and therefore are still vulnerable to the errors in the redundant circuitry added for error-tolerance. This paper proposes a novel self-checking soft error-tolerant register based on SETTOFF, a Soft Error and Timing error Tolerant Flip-Flop. The register significantly improves the error-tolerant capability over previous techniques since it has a self-checking capability, which allows the register to tolerate both the errors in the original flip-flops and the redundant circuitry. In addition, the register can also tolerate both soft errors (SETs and SEUs) and timing errors. Compared with other previous techniques such as TMR, the proposed register reduces the power consumption overhead by 81%, and the delay overhead by 54% in 65nm technology; The area overhead is also reduced by 25%

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More information

Published date: June 2014
Venue - Dates: International Symposium on Circuits and Systems, Australia, 2014-06-01 - 2014-06-05
Organisations: EEE

Identifiers

Local EPrints ID: 365109
URI: http://eprints.soton.ac.uk/id/eprint/365109
PURE UUID: 61414569-34e0-49b9-b7db-f29b6cad86c5
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 23 May 2014 09:20
Last modified: 19 Nov 2019 02:02

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