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Silicon photonic integration platform - have we found the sweet spot?

Silicon photonic integration platform - have we found the sweet spot?
Silicon photonic integration platform - have we found the sweet spot?
The current trend in silicon photonics towards higher levels of integration as well as the model of using CMOS foundries for fabrication are leading to a need for standardization of substrate parameters and fabrication processes. In particular, for several established research and development foundries that grant general access, silicon-on-insulator wafers with a silicon thickness of 220nm have become the standard substrate for which devices and circuits have to be designed. In this study we investigate the role of silicon device layer thickness in design optimization of various components that need to be integrated in a typical optical transceiver, including both passive ones for routing, wavelength selection, and light coupling as well as active ones such as monolithic modulators and on-chip lasers produced by hybrid integration. We find that in all devices considered there is an advantage in using a silicon thickness larger than 220nm, either for improved performance or for simplified fabrication processes and relaxed tolerances.
1077-260X
189-205
Xu, Dan-Xia
49b8b606-0aea-444d-842e-4ada1f9bbce8
Schmid, Jens H.
de954bee-9975-423f-8e10-0d35a4759f02
Reed, Graham T.
ca08dd60-c072-4d7d-b254-75714d570139
Mashanovich, Goran Z.
c806e262-af80-4836-b96f-319425060051
Thomson, David J.
17c1626c-2422-42c6-98e0-586ae220bcda
Nedeljković, Milos
b64e21c2-1b95-479d-a35c-3456dff8c796
Chen, Xia
64f6ab92-ca11-4489-8c03-52bc986209ae
Van Thourhout, Dries
611246e8-7eda-48f2-bc9b-9eecd1315182
Keyvaninia, Shahram
ed57d481-ff99-4e13-b986-3e5b84cc4fc1
Selvaraja, Shankar K.
85b00647-9e60-472f-87d5-14e202497b6e
Xu, Dan-Xia
49b8b606-0aea-444d-842e-4ada1f9bbce8
Schmid, Jens H.
de954bee-9975-423f-8e10-0d35a4759f02
Reed, Graham T.
ca08dd60-c072-4d7d-b254-75714d570139
Mashanovich, Goran Z.
c806e262-af80-4836-b96f-319425060051
Thomson, David J.
17c1626c-2422-42c6-98e0-586ae220bcda
Nedeljković, Milos
b64e21c2-1b95-479d-a35c-3456dff8c796
Chen, Xia
64f6ab92-ca11-4489-8c03-52bc986209ae
Van Thourhout, Dries
611246e8-7eda-48f2-bc9b-9eecd1315182
Keyvaninia, Shahram
ed57d481-ff99-4e13-b986-3e5b84cc4fc1
Selvaraja, Shankar K.
85b00647-9e60-472f-87d5-14e202497b6e

Xu, Dan-Xia, Schmid, Jens H., Reed, Graham T., Mashanovich, Goran Z., Thomson, David J., Nedeljković, Milos, Chen, Xia, Van Thourhout, Dries, Keyvaninia, Shahram and Selvaraja, Shankar K. (2014) Silicon photonic integration platform - have we found the sweet spot? IEEE Journal of Selected Topics in Quantum Electronics, 20 (4), 189-205. (doi:10.1109/JSTQE.2014.2299634).

Record type: Article

Abstract

The current trend in silicon photonics towards higher levels of integration as well as the model of using CMOS foundries for fabrication are leading to a need for standardization of substrate parameters and fabrication processes. In particular, for several established research and development foundries that grant general access, silicon-on-insulator wafers with a silicon thickness of 220nm have become the standard substrate for which devices and circuits have to be designed. In this study we investigate the role of silicon device layer thickness in design optimization of various components that need to be integrated in a typical optical transceiver, including both passive ones for routing, wavelength selection, and light coupling as well as active ones such as monolithic modulators and on-chip lasers produced by hybrid integration. We find that in all devices considered there is an advantage in using a silicon thickness larger than 220nm, either for improved performance or for simplified fabrication processes and relaxed tolerances.

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Accepted/In Press date: 31 December 2013
e-pub ahead of print date: 10 January 2014
Published date: July 2014
Organisations: Optoelectronics Research Centre, Electronics & Computer Science, Photonic Systems Circuits & Sensors

Identifiers

Local EPrints ID: 367864
URI: https://eprints.soton.ac.uk/id/eprint/367864
ISSN: 1077-260X
PURE UUID: 1c16e0f2-2b35-417a-ae10-8482fb0eda66
ORCID for Milos Nedeljković: ORCID iD orcid.org/0000-0002-9170-7911
ORCID for Xia Chen: ORCID iD orcid.org/0000-0002-0994-5401

Catalogue record

Date deposited: 08 Aug 2014 10:04
Last modified: 03 Dec 2019 01:37

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Contributors

Author: Dan-Xia Xu
Author: Jens H. Schmid
Author: Graham T. Reed
Author: Milos Nedeljković ORCID iD
Author: Xia Chen ORCID iD
Author: Dries Van Thourhout
Author: Shahram Keyvaninia
Author: Shankar K. Selvaraja

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