Low-cost on-chip clock jitter measurement scheme
Low-cost on-chip clock jitter measurement scheme
In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution.
1-9
Omana, Martin
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Rossi, Daniele
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Giaffreda, Daniele
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Metra, Cecilia
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Mak, T.M.
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Raman, Asifur
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Tam, Simon
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11 April 2014
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Giaffreda, Daniele
2d39689b-2783-48cb-aec7-9235900856c2
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Mak, T.M.
452aaf4a-4fae-426b-92cc-b8437998d3e3
Raman, Asifur
64fec427-1adf-4441-bfa8-54772006c438
Tam, Simon
4552c758-5e16-4dba-a6ab-8c711090f5b4
Omana, Martin, Rossi, Daniele, Giaffreda, Daniele, Metra, Cecilia, Mak, T.M., Raman, Asifur and Tam, Simon
(2014)
Low-cost on-chip clock jitter measurement scheme.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, .
(doi:10.1109/TVLSI.2014.2312431).
Abstract
In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution.
Text
tvlsi14-jitter.pdf
- Accepted Manuscript
More information
e-pub ahead of print date: 23 February 2014
Published date: 11 April 2014
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 368663
URI: http://eprints.soton.ac.uk/id/eprint/368663
ISSN: 1063-8210
PURE UUID: 3deb2f04-bdb9-420d-a435-9f173aa80dae
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Date deposited: 11 Sep 2014 09:01
Last modified: 14 Mar 2024 17:51
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Contributors
Author:
Martin Omana
Author:
Daniele Rossi
Author:
Daniele Giaffreda
Author:
Cecilia Metra
Author:
T.M. Mak
Author:
Asifur Raman
Author:
Simon Tam
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