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Model for transient fault susceptibility of combinational circuits

Model for transient fault susceptibility of combinational circuits
Model for transient fault susceptibility of combinational circuits
Transient faults (TFs) are increasingly affecting microelectronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional electrical level simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a new model to estimate accurately the possible propagation of transient fault-due glitches through a CMOS combinational circuit. We will show how the proposed model can be applied in order to estimate the TF susceptibility of a circuit by simply considering the propagation delay of the datapath. Therefore, the proposed model is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to electrical level simulation. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations.
0923-8174
501-509
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2004) Model for transient fault susceptibility of combinational circuits. Journal of Electronic Testing, Theory and Applications (JETTA), 20 (5), 501-509.

Record type: Article

Abstract

Transient faults (TFs) are increasingly affecting microelectronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional electrical level simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a new model to estimate accurately the possible propagation of transient fault-due glitches through a CMOS combinational circuit. We will show how the proposed model can be applied in order to estimate the TF susceptibility of a circuit by simply considering the propagation delay of the datapath. Therefore, the proposed model is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to electrical level simulation. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations.

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Published date: October 2004
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 368672
URI: https://eprints.soton.ac.uk/id/eprint/368672
ISSN: 0923-8174
PURE UUID: 11496c61-221a-46fc-8efc-5ec516362b3d

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Date deposited: 22 Sep 2014 12:17
Last modified: 30 Oct 2017 12:58

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