A model for transient fault propagation in combinatorial logic
A model for transient fault propagation in combinatorial logic
Transient faults (TFs) are increasingly affecting micro-electronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional HSPICE like simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a novel mathematical model to accurately estimate the possible propagation of transient fault-due glitches through a CMOS combinational circuit, which is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to HPSICE. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations
0-7695-1968-7
111-115
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Papasso, Giacinto
3c4eaf70-b58e-4fc1-904f-9a38cb125d40
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
July 2003
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Papasso, Giacinto
3c4eaf70-b58e-4fc1-904f-9a38cb125d40
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Omana, Martin, Papasso, Giacinto, Rossi, Daniele and Metra, Cecilia
(2003)
A model for transient fault propagation in combinatorial logic.
9th IEEE International On-Line Testing Symposium, Kos Island, Greece.
07 - 09 Jul 2003.
.
(doi:10.1109/OLT.2003.1214376).
Record type:
Conference or Workshop Item
(Paper)
Abstract
Transient faults (TFs) are increasingly affecting micro-electronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional HSPICE like simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a novel mathematical model to accurately estimate the possible propagation of transient fault-due glitches through a CMOS combinational circuit, which is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to HPSICE. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations
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Published date: July 2003
Venue - Dates:
9th IEEE International On-Line Testing Symposium, Kos Island, Greece, 2003-07-07 - 2003-07-09
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 368875
URI: http://eprints.soton.ac.uk/id/eprint/368875
ISBN: 0-7695-1968-7
PURE UUID: d8816238-aca0-4494-994d-aef5cc2bbff0
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Date deposited: 06 Oct 2014 11:44
Last modified: 14 Mar 2024 17:55
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Contributors
Author:
Martin Omana
Author:
Giacinto Papasso
Author:
Daniele Rossi
Author:
Cecilia Metra
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