Error correcting codes for crosstalk effect minimization [system buses]
Error correcting codes for crosstalk effect minimization [system buses]
In this paper, we present an analysis of crosstalk effects on buses implementing error correcting codes. We show that the redundancy introduced by these codes can be exploited in order to avoid the worst case crosstalk-induced delay. Our analysis is based on the evaluation of the coupling effective capacitance which needs to be charged during bus activity. In particular, we analyze the cases of the Hamming and dual rail codes. We show that Hamming codes do not allow us to avoid the most delay costly bus transitions, while this can be the case for dual rail codes. Furthermore, we illustrate that, by increasing the redundancy of the dual rail code by only one bit, even higher crosstalk-induced delay reductions can be achieved. Finally, we show that a further improvement can be obtained by an optimized placing of the bus wires.
0-7695-2042-1
257-264
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Cavallotti, Stefano
b6520432-b08c-40a5-ab26-d5f414065805
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
November 2003
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Cavallotti, Stefano
b6520432-b08c-40a5-ab26-d5f414065805
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Rossi, Daniele, Cavallotti, Stefano and Metra, Cecilia
(2003)
Error correcting codes for crosstalk effect minimization [system buses].
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, United States.
03 - 05 Nov 2003.
.
(doi:10.1109/DFTVS.2003.1250120).
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Conference or Workshop Item
(Paper)
Abstract
In this paper, we present an analysis of crosstalk effects on buses implementing error correcting codes. We show that the redundancy introduced by these codes can be exploited in order to avoid the worst case crosstalk-induced delay. Our analysis is based on the evaluation of the coupling effective capacitance which needs to be charged during bus activity. In particular, we analyze the cases of the Hamming and dual rail codes. We show that Hamming codes do not allow us to avoid the most delay costly bus transitions, while this can be the case for dual rail codes. Furthermore, we illustrate that, by increasing the redundancy of the dual rail code by only one bit, even higher crosstalk-induced delay reductions can be achieved. Finally, we show that a further improvement can be obtained by an optimized placing of the bus wires.
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Published date: November 2003
Venue - Dates:
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, United States, 2003-11-03 - 2003-11-05
Organisations:
Electronic & Software Systems
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Local EPrints ID: 368881
URI: http://eprints.soton.ac.uk/id/eprint/368881
ISBN: 0-7695-2042-1
PURE UUID: 50e09f8a-da33-4594-bc75-ed71c72f6bfc
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Date deposited: 08 Oct 2014 10:58
Last modified: 14 Mar 2024 17:55
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Contributors
Author:
Daniele Rossi
Author:
Stefano Cavallotti
Author:
Cecilia Metra
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