Fast and low-cost clock deskew buffer
Fast and low-cost clock deskew buffer
We propose a clock buffer that is able to compensate clock skews possibly due to process variations, and correct even more severe skews, as those possibly due to faults affecting the clock distribution network or those due to power supply noise. Compensation/correction is performed instantaneously, during system run-time, upon skew occurrence. Compared to alternative solutions which can be used to compensate/correct skews between couples of clocks, that presented here is definitely faster, features lower area overhead and power consumption, and does not require any initialization phase at the beginning of system operation. Additionally, our proposed buffer is also able to compensate/correct clock duty cycle variations due to process parameter variations, as well as faults affecting the clock distribution network. Also in this case, compensation/correction is accomplished within the same clock cycle of duty-cycle variation occurrence.
0-7695-2241-6
202-210
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
October 2004
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Omana, Martin, Rossi, Daniele and Metra, Cecilia
(2004)
Fast and low-cost clock deskew buffer.
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2004). Proceedings, Cannes, France.
10 - 13 Oct 2004.
.
(doi:10.1109/DFTVS.2004.1347841).
Record type:
Conference or Workshop Item
(Paper)
Abstract
We propose a clock buffer that is able to compensate clock skews possibly due to process variations, and correct even more severe skews, as those possibly due to faults affecting the clock distribution network or those due to power supply noise. Compensation/correction is performed instantaneously, during system run-time, upon skew occurrence. Compared to alternative solutions which can be used to compensate/correct skews between couples of clocks, that presented here is definitely faster, features lower area overhead and power consumption, and does not require any initialization phase at the beginning of system operation. Additionally, our proposed buffer is also able to compensate/correct clock duty cycle variations due to process parameter variations, as well as faults affecting the clock distribution network. Also in this case, compensation/correction is accomplished within the same clock cycle of duty-cycle variation occurrence.
Text
dfts04.pdf
- Version of Record
Restricted to Repository staff only
Request a copy
More information
Published date: October 2004
Venue - Dates:
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2004). Proceedings, Cannes, France, 2004-10-10 - 2004-10-13
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 368884
URI: http://eprints.soton.ac.uk/id/eprint/368884
ISBN: 0-7695-2241-6
PURE UUID: 20ee3fd2-0e75-408a-a520-ef2ced4191e9
Catalogue record
Date deposited: 08 Oct 2014 11:26
Last modified: 14 Mar 2024 17:55
Export record
Altmetrics
Contributors
Author:
Martin Omana
Author:
Daniele Rossi
Author:
Cecilia Metra
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.
View more statistics