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Low cost scheme for on-line clock skew compensation

Low cost scheme for on-line clock skew compensation
Low cost scheme for on-line clock skew compensation
In this paper we propose a novel buffer scheme that is able to compensate undesired skews between clocks of a synchronous system in a negligible time upon skew occurrence, thus being suitable also for on-line clock-skew correction. Clock signals are aligned one with respect to the other, starting from a reference clock, and moving forward among physically adjacent clock signals, thus creating no problem of reference clock's routing. Our solution is also able to compensate clock duty-cycle variations, which have been shown very likely in case of faults, for instance bridgings, affecting the clock distribution network. Compared to alternate solutions, our proposed scheme enables significant reductions in area overhead and power consumption, and is suitable for on-line compensation. Therefore, it allows clock skew and duty-cycle fault tolerance, thus increasing process yield and system's reliability.
0-7695-2314-5
90-95
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2005) Low cost scheme for on-line clock skew compensation. 23rd IEEE VLSI Test Symposium. Proceedings, Palm Springs, United States. 01 - 05 May 2005. pp. 90-95 . (doi:10.1109/VTS.2005.52).

Record type: Conference or Workshop Item (Paper)

Abstract

In this paper we propose a novel buffer scheme that is able to compensate undesired skews between clocks of a synchronous system in a negligible time upon skew occurrence, thus being suitable also for on-line clock-skew correction. Clock signals are aligned one with respect to the other, starting from a reference clock, and moving forward among physically adjacent clock signals, thus creating no problem of reference clock's routing. Our solution is also able to compensate clock duty-cycle variations, which have been shown very likely in case of faults, for instance bridgings, affecting the clock distribution network. Compared to alternate solutions, our proposed scheme enables significant reductions in area overhead and power consumption, and is suitable for on-line compensation. Therefore, it allows clock skew and duty-cycle fault tolerance, thus increasing process yield and system's reliability.

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Published date: May 2005
Venue - Dates: 23rd IEEE VLSI Test Symposium. Proceedings, Palm Springs, United States, 2005-05-01 - 2005-05-05
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 368885
URI: http://eprints.soton.ac.uk/id/eprint/368885
ISBN: 0-7695-2314-5
PURE UUID: 771ea36a-7246-44f9-9283-27bdd3086b01

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Date deposited: 08 Oct 2014 12:07
Last modified: 14 Mar 2024 17:55

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Contributors

Author: Martin Omana
Author: Daniele Rossi
Author: Cecilia Metra

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