On-transistor level gate sizing for increased robustness to transient faults
On-transistor level gate sizing for increased robustness to transient faults
In this paper we present a detailed analysis on how the critical charge (Qcrit) of a circuit node, usually employed to evaluate the probability of transient fault (TF) occurrence as a consequence of a particle hit, depends on transistors' sizing. We derive an analytical model allowing us to calculate a node's Qcrit given the size of the node's driving gate and fan-out gate(s), thus avoiding time costly electrical level simulations. We verified that such a model features an accuracy of the 97% with respect to electrical level simulations performed by HSPICE. Our proposed model shows that Qcrit depends much more on the strength (conductance) of the gate driving the node, than on the node total capacitance. We also evaluated the impact of increasing the conductance of the driving gate on TFs' propagation, hence on soft error susceptibility (SES). We found that such a conductance increase not only improves the TF robustness of the hardened node, but also that of the whole circuit.
0-7695-2406-0
23-28
Cazeaux, Jose Manuel
56eb0eda-d852-43af-9227-054d92e9f755
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Chatterjee, Abhijit
5785aea1-e251-4ce2-92c7-57c6263a1543
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
July 2005
Cazeaux, Jose Manuel
56eb0eda-d852-43af-9227-054d92e9f755
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Chatterjee, Abhijit
5785aea1-e251-4ce2-92c7-57c6263a1543
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Cazeaux, Jose Manuel, Rossi, Daniele, Omana, Martin, Chatterjee, Abhijit and Metra, Cecilia
(2005)
On-transistor level gate sizing for increased robustness to transient faults.
11th IEEE International On-Line Testing Symposium (IOLTS 2005), Saint Raphael, France.
06 - 08 Jul 2005.
.
(doi:10.1109/IOLTS.2005.49).
Record type:
Conference or Workshop Item
(Paper)
Abstract
In this paper we present a detailed analysis on how the critical charge (Qcrit) of a circuit node, usually employed to evaluate the probability of transient fault (TF) occurrence as a consequence of a particle hit, depends on transistors' sizing. We derive an analytical model allowing us to calculate a node's Qcrit given the size of the node's driving gate and fan-out gate(s), thus avoiding time costly electrical level simulations. We verified that such a model features an accuracy of the 97% with respect to electrical level simulations performed by HSPICE. Our proposed model shows that Qcrit depends much more on the strength (conductance) of the gate driving the node, than on the node total capacitance. We also evaluated the impact of increasing the conductance of the driving gate on TFs' propagation, hence on soft error susceptibility (SES). We found that such a conductance increase not only improves the TF robustness of the hardened node, but also that of the whole circuit.
Text
iolts05-tf.pdf
- Version of Record
Restricted to Repository staff only
Request a copy
More information
Published date: July 2005
Venue - Dates:
11th IEEE International On-Line Testing Symposium (IOLTS 2005), Saint Raphael, France, 2005-07-06 - 2005-07-08
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 368887
URI: http://eprints.soton.ac.uk/id/eprint/368887
ISBN: 0-7695-2406-0
PURE UUID: 0abac225-9c41-47c3-bfa6-6a13dbcfbaf7
Catalogue record
Date deposited: 08 Oct 2014 12:11
Last modified: 14 Mar 2024 17:55
Export record
Altmetrics
Contributors
Author:
Jose Manuel Cazeaux
Author:
Daniele Rossi
Author:
Martin Omana
Author:
Abhijit Chatterjee
Author:
Cecilia Metra
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.
View more statistics