The other side of the timing equation: a result of clock faults

Metra, Cecilia, Omana, Martin, Rossi, Daniele, Cazeaux, Jose' Manuel and Mak, T.M. (2005) The other side of the timing equation: a result of clock faults. 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2005), Monterey, United States. 03 - 05 Oct 2005. pp. 169-177 . (doi:10.1109/DFTVS.2005.65).

Record type: Conference or Workshop Item (Paper)

Abstract

We analyze the impact of clock faults on product quality and operation in the field. We show that clock faults could: i) give rise to min delay violations; ii) compromise the effectiveness of delay fault testing in screening out possible delay faults; iii) be missed by current functional testing (in addition to possibly be missed by structural testing, as proven by Metra et al. (2004). Therefore, new testing/DFT approaches are needed to avoid the dramatic impact of clock faults on product quality and operation in the field. Various possible approaches are discussed.

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Published date: November 2005

Venue - Dates: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2005), Monterey, United States, 2005-10-03 - 2005-10-05

Organisations: Electronic & Software Systems

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