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Path (min) delay faults and their impact on self-checking circuits’ operation

Path (min) delay faults and their impact on self-checking circuits’ operation
Path (min) delay faults and their impact on self-checking circuits’ operation
Min delay violations are traditionally not modeled as possible faults as a result of manufacturing defects. Usually, path delay faults are implicitly assumed to be paths' max delay violations. This, in turn, is based on the assumption that min delay violations are designed out. Most previous manufacturing defect/fault analysis works have not considered their effect on clock circuits. More recently, as burn-in becomes ineffective and process variations become more of an issue, latent defects, device degradation or wear out in the field would potentially also cripple the clock distribution network. Consequently, we should start considering also path (min) delay faults when designing on-line testable circuits, similar to what we currently do for path (max) delay faults. The challenges that this poses to the existing on-line testing strategies are discussed. Examples showing the possible incorrect behavior of a self-checking circuit as a result of this kind of faults are given. New on-line testing strategies should consequently be devised to deal with these faults
0-7695-2620-9
17-22
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Cazeaux, Jose Manuel
56eb0eda-d852-43af-9227-054d92e9f755
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Cazeaux, Jose Manuel
56eb0eda-d852-43af-9227-054d92e9f755

Metra, Cecilia, Omana, Martin, Rossi, Daniele and Cazeaux, Jose Manuel (2006) Path (min) delay faults and their impact on self-checking circuits’ operation. 12th IEEE International On-Line Testing Symposium, 2006. IOLTS 2006, Como, Italy. pp. 17-22 . (doi:10.1109/IOLTS.2006.47).

Record type: Conference or Workshop Item (Paper)

Abstract

Min delay violations are traditionally not modeled as possible faults as a result of manufacturing defects. Usually, path delay faults are implicitly assumed to be paths' max delay violations. This, in turn, is based on the assumption that min delay violations are designed out. Most previous manufacturing defect/fault analysis works have not considered their effect on clock circuits. More recently, as burn-in becomes ineffective and process variations become more of an issue, latent defects, device degradation or wear out in the field would potentially also cripple the clock distribution network. Consequently, we should start considering also path (min) delay faults when designing on-line testable circuits, similar to what we currently do for path (max) delay faults. The challenges that this poses to the existing on-line testing strategies are discussed. Examples showing the possible incorrect behavior of a self-checking circuit as a result of this kind of faults are given. New on-line testing strategies should consequently be devised to deal with these faults

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Published date: July 2006
Venue - Dates: 12th IEEE International On-Line Testing Symposium, 2006. IOLTS 2006, Como, Italy, 2006-07-01
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 368900
URI: http://eprints.soton.ac.uk/id/eprint/368900
ISBN: 0-7695-2620-9
PURE UUID: db161725-10ba-4736-945d-1f05521cd7b6

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Date deposited: 06 Oct 2014 13:35
Last modified: 14 Mar 2024 17:55

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Contributors

Author: Cecilia Metra
Author: Martin Omana
Author: Daniele Rossi
Author: Jose Manuel Cazeaux

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