Function-inherent code checking: a new low cost on-line testing approach for high performance microprocessor control logic
Function-inherent code checking: a new low cost on-line testing approach for high performance microprocessor control logic
We propose an on-line testing approach for the control logic of high performance microprocessors. Rather than adding information redundancy (in the form of error detecting codes), we propose to look for the information redundancy (referred to as Function-Inherent Codes) that the microprocessor control logic may inherently have, due to its required functionality. We will show that this allows to achieve on-line testing at significant savings in terms of area and power consumption, and with lower or comparable impact on system performance and design costs, compared to alternate, traditional on-line testing approaches.
on-line testing, control logic, microprocessor, error detecting codes
978-0-7695-3150-2
171-176
Metra, Cecilia
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Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Omana, Martin
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Jas, Abhijit
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Galivanche, Rajesh
344d42dd-a120-4720-9c8e-56e4b13007ca
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Jas, Abhijit
5eccda6f-0b46-4645-9088-92fdcbf87af5
Galivanche, Rajesh
344d42dd-a120-4720-9c8e-56e4b13007ca
Metra, Cecilia, Rossi, Daniele, Omana, Martin, Jas, Abhijit and Galivanche, Rajesh
(2008)
Function-inherent code checking: a new low cost on-line testing approach for high performance microprocessor control logic.
IEEE European Test Symposium, Verbania, Italy.
25 - 29 May 2008.
.
(doi:10.1109/ETS.2008.24).
Record type:
Conference or Workshop Item
(Paper)
Abstract
We propose an on-line testing approach for the control logic of high performance microprocessors. Rather than adding information redundancy (in the form of error detecting codes), we propose to look for the information redundancy (referred to as Function-Inherent Codes) that the microprocessor control logic may inherently have, due to its required functionality. We will show that this allows to achieve on-line testing at significant savings in terms of area and power consumption, and with lower or comparable impact on system performance and design costs, compared to alternate, traditional on-line testing approaches.
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e-pub ahead of print date: May 2008
Venue - Dates:
IEEE European Test Symposium, Verbania, Italy, 2008-05-25 - 2008-05-29
Keywords:
on-line testing, control logic, microprocessor, error detecting codes
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 368904
URI: http://eprints.soton.ac.uk/id/eprint/368904
ISBN: 978-0-7695-3150-2
PURE UUID: f3d04d0a-47c1-4e2b-8490-1e0d3e38c206
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Date deposited: 17 Sep 2014 10:39
Last modified: 14 Mar 2024 17:55
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Contributors
Author:
Cecilia Metra
Author:
Daniele Rossi
Author:
Martin Omana
Author:
Abhijit Jas
Author:
Rajesh Galivanche
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