Resistive crossbar switching networks for inherently fault tolerant nano LUTs
Resistive crossbar switching networks for inherently fault tolerant nano LUTs
We present a detailed treatment of Crossbar Switching Networks (R-CSNs) made of resistive elements for memory utilization (as look-up table) in a nano FPGA. Initially, a technology assessment of this technology compared with a VLSI CMOS based memory is pursued considering area and support circuitry. Then, a graph model is utilized for characterizing the effects of a single fault on the fault tolerant capabilities of a R-CSN. This is used to establish the exact analytical expression for the fault tolerance of a R-CSN in the presence of a single stuck-open/closed fault. The presented analysis confirms that small-sized R-CSNs are well suited as LUTs for FPGAs at nano scales.
978-0-7695-3379-7
21-24
Ma, X.
36839bb1-f01f-4e00-b113-b6914c3d0d64
Huang, F.
da2bba71-decd-4d0a-9ba6-0ed12e1bd256
Chiminazzo, Federica
5c92159e-e86e-4c73-a1e8-377bafd3e016
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Lombardi, Fabrizio
e36a0194-d0fc-443b-82c5-72cefd730b0f
Ma, X.
36839bb1-f01f-4e00-b113-b6914c3d0d64
Huang, F.
da2bba71-decd-4d0a-9ba6-0ed12e1bd256
Chiminazzo, Federica
5c92159e-e86e-4c73-a1e8-377bafd3e016
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Lombardi, Fabrizio
e36a0194-d0fc-443b-82c5-72cefd730b0f
Ma, X., Huang, F., Chiminazzo, Federica, Rossi, Daniele, Metra, Cecilia and Lombardi, Fabrizio
(2008)
Resistive crossbar switching networks for inherently fault tolerant nano LUTs.
2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems, Cambridge, United States.
29 - 30 Sep 2008.
.
(doi:10.1109/NDCS.2008.21).
Record type:
Conference or Workshop Item
(Paper)
Abstract
We present a detailed treatment of Crossbar Switching Networks (R-CSNs) made of resistive elements for memory utilization (as look-up table) in a nano FPGA. Initially, a technology assessment of this technology compared with a VLSI CMOS based memory is pursued considering area and support circuitry. Then, a graph model is utilized for characterizing the effects of a single fault on the fault tolerant capabilities of a R-CSN. This is used to establish the exact analytical expression for the fault tolerance of a R-CSN in the presence of a single stuck-open/closed fault. The presented analysis confirms that small-sized R-CSNs are well suited as LUTs for FPGAs at nano scales.
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e-pub ahead of print date: September 2008
Venue - Dates:
2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems, Cambridge, United States, 2008-09-29 - 2008-09-30
Organisations:
Electronic & Software Systems
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Local EPrints ID: 368906
URI: http://eprints.soton.ac.uk/id/eprint/368906
ISBN: 978-0-7695-3379-7
PURE UUID: 559d85ef-6589-4b51-a507-6f0a30f03ad9
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Date deposited: 17 Sep 2014 10:34
Last modified: 14 Mar 2024 17:56
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Contributors
Author:
X. Ma
Author:
F. Huang
Author:
Federica Chiminazzo
Author:
Daniele Rossi
Author:
Cecilia Metra
Author:
Fabrizio Lombardi
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