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Fault tolerant high performance Galios field arithmetic processor

Fault tolerant high performance Galios field arithmetic processor
Fault tolerant high performance Galios field arithmetic processor
Reliability is an emerging design requirement for finite field processors used in cryptographic systems. However, reliable design of these systems is particularly challenging due to conflicting design requirements, including high performance and low power consumption. In this paper, we propose a novel design technique for reliable and low power Galois field (GF) arithmetic processor. The aim is to tolerate faults in the GF processor during on-line computation at reduced system costs, while maintaining high performance. The reduction in system costs is achieved through multiple parity prediction and comparison considering the trade-offs between performance and complexity. The effectiveness of the proposed technique is then validated using a case study of 163-bit digit serial multipliers using 90nm and 180nm technology nodes highlighting the resulting area, latency and power overheads. We show that up to 40 stuck-at faults can be tolerated during computation with reasonable system area and power costs.
978-3-642-32111-5
305
269-281
Springer
Narayanan, V.K.
94db7ead-3ec8-483a-a127-0819882c3841
Shafik, R.A.
aa0bdafc-b022-4cb2-a8ef-4bf8a03ba524
Mathew, Jimson
156eec1e-d690-43eb-a72f-daefd8b04144
Pradhan, D.K.
2d22b279-67de-4ebd-ae43-0687f35530d6
Mathew, Jimson
Patra, Priyadarshan
Pradhan, D.K.
Kuttyamma, A.J.
Narayanan, V.K.
94db7ead-3ec8-483a-a127-0819882c3841
Shafik, R.A.
aa0bdafc-b022-4cb2-a8ef-4bf8a03ba524
Mathew, Jimson
156eec1e-d690-43eb-a72f-daefd8b04144
Pradhan, D.K.
2d22b279-67de-4ebd-ae43-0687f35530d6
Mathew, Jimson
Patra, Priyadarshan
Pradhan, D.K.
Kuttyamma, A.J.

Narayanan, V.K., Shafik, R.A., Mathew, Jimson and Pradhan, D.K. (2012) Fault tolerant high performance Galios field arithmetic processor. In, Mathew, Jimson, Patra, Priyadarshan, Pradhan, D.K. and Kuttyamma, A.J. (eds.) Eco-friendly Computing and Communication Systems: International Conference, ICECCS 2012, Kochi, India, August 9-11, 2012. (Communications in Computer and Information Science, , (doi:10.1007/978-3-642-32112-2_33), 305) Heidelberg, DE. Springer, pp. 269-281. (doi:10.1007/978-3-642-32112-2_33).

Record type: Book Section

Abstract

Reliability is an emerging design requirement for finite field processors used in cryptographic systems. However, reliable design of these systems is particularly challenging due to conflicting design requirements, including high performance and low power consumption. In this paper, we propose a novel design technique for reliable and low power Galois field (GF) arithmetic processor. The aim is to tolerate faults in the GF processor during on-line computation at reduced system costs, while maintaining high performance. The reduction in system costs is achieved through multiple parity prediction and comparison considering the trade-offs between performance and complexity. The effectiveness of the proposed technique is then validated using a case study of 163-bit digit serial multipliers using 90nm and 180nm technology nodes highlighting the resulting area, latency and power overheads. We show that up to 40 stuck-at faults can be tolerated during computation with reasonable system area and power costs.

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Published date: August 2012
Organisations: Electronics & Computer Science

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Local EPrints ID: 369407
URI: http://eprints.soton.ac.uk/id/eprint/369407
ISBN: 978-3-642-32111-5
PURE UUID: 6f88d816-4f16-4e6a-9f4b-7cfb7bb4d044

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Date deposited: 01 Oct 2014 12:34
Last modified: 15 Jul 2019 21:43

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Contributors

Author: V.K. Narayanan
Author: R.A. Shafik
Author: Jimson Mathew
Author: D.K. Pradhan
Editor: Jimson Mathew
Editor: Priyadarshan Patra
Editor: D.K. Pradhan
Editor: A.J. Kuttyamma

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