Development of low temperature fabrication processes of n-ZnO/p-Si optical switch and poly-silicon waveguides for CMOS-compatible multi-layered silicon photonics

Abstract

The potential advantages and applications of Silicon Photonics (SiP) has initiated substantial research efforts. Silicon photonics has been favourably nominated to replace the current copper interconnects due to their high bandwidth, small footprint, and potentially low power consumption. However, the majority of the research into silicon photonics has been based on the silicon-on insulator (SOI) platform. The focus on the SOI platform has limited the design of silicon photonic devices to two-dimensional (2D) structures. Moreover, the fabrication of optical active devices based on silicon photonics has relied on high temperature processing that is not compatible with CMOS back-end integration. New materials that are depositable at low temperatures can offer new possibilities for multi-layered, CMOS back-end compatible, and low optical loss silicon photonic devices. In this project, zinc oxide (ZnO) was investigated as a potential low temperature material whose fabrication is compatible with CMOS technology. Specifically, the naturally n-type doped ZnO can potentially form a heterojunction with p-type silicon without the need for high temperature processing. Poly-silicon is also a depositable and CMOS compatible material that can potentially form future multi-layered silicon photonic structures. However, low optical loss in poly-silicon has been based on high-temperature processing to improve the crystallinity and roughness of the deposited material. The deposition of poly-silicon in the SiP technology have been mainly carried out using plasma-enhanced chemical vapour deposition (PECVD) and other deposition techniques remain under investigated.
In this project, ZnO was, for the first time, deposited at low-temperature (150 ºC) using atomic layer deposition (ALD) on a silicon waveguide to form a heterojunction diode capable of producing optical switching in the silicon core. Optical switching in the n-ZnO/p-Si heterojunction was caused by the plasma dispersion effect. The design of the optical switch comprised a straight silicon waveguide (width = 1000 nm, height = 220 nm, slabheight = 60 nm) partially covered with a thin ZnO film (thickness = 10 nm). The commonly used highly doped p+ region were not included in the devices because of the high thermal budget (T ' 900 ºC) needed to activate the dopant. Moreover, the aluminium (Al) metal contacts were not annealed because the annealing temperature (Ts = 425ºC) exceeds the high-temperature threshold (Ts = 400?C). An extinction ratio of ~ 10 dB was achieved for a 1 mm long device at 20 V forward-bias. This result can be expressed as a figure of merit of 5 dB/cm.V. The insertion loss of the device was estimated to be ~ 1:2 dB. The maximum switching speed of the devices was found to be ~1 MHz. Al-though this performance is inferior to the state-of-the-art silicon optical switches, it offers the first silicon-based electro-optical switch fabricated at low-temperatures with low insertion loss. Detailed analysis of the I-V and switching characteristics of the device revealed large series resistance and capacitance. It was also found that the switching speed is primarily governed by the RC time constant of the device rather than the minority carrier lifetime. This fact has led us to believe that the device functions as both injection and accumulation electro-absorption switch. A thin SiO₂ layer is suspected to form at the ZnO/Si interface that facilitates the accumulation operation of the device and increases the RC time constant.
The first low loss and low-temperature poly-silicon waveguides are demonstrated in this project. Hot-wire chemical vapour deposition (HWCVD) was used to deposit poly-silicon films at 240?C. The propagation loss of the TE mode for a 600 by 220 nm waveguide was 13:5 dB/cm. Detailed simulation analysis revealed that at least 60% of the loss was caused by the roughness of the top surface of the waveguides. The RMS roughness was measured using atomic force microscopy (AFM) and was found to be 8:9 nm. Optimisation of the design, the deposition process, and the reduction of the top surface roughness, through surface planarisation, led to a reduction in the propagation loss of the TE mode to ~8:5 dB/cm while still maintaining low deposition temperature of 360ºC. The crystal volume fraction of the optimised poly-silicon film was found to be ~96%. An electro-optical switch based on ZnO and poly-silicon heterojunction was fabricated on a multi-layered poly silicon structure. However, there were problems with the metal contact pads as well as the thickness of the first poly-silicon layer. Future work will focus on improving the n-ZnO/p-Si heterojunction electro-optical performance by adapting an accumulation type structure as well as optimising the multi-layered poly-silicon platform.

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ORCID for H M H Chong: orcid.org/0000-0002-7110-5761

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