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A unified design methodology for secure test and IP core protection

A unified design methodology for secure test and IP core protection
A unified design methodology for secure test and IP core protection
On-chip security is an emerging challenge in the design of embedded systems with intellectual property (IP) cores. Traditionally this challenge is addressed using ad hoc design techniques with separate design objectives of secure design for testability (DfT), and IP core protection. However, in this paper, we will argue that such design approaches can incur high costs. Underpinning this argument, we propose a novel design methodology, called Secure TEst and IP core Protection (STEP), which aims to address the joint objective of IP core protection and secure testing. To ensure that this objective is achieved at a low cost, the STEP design methodology employs common key integrated hardware. This hardware is incorporated in the system through an automated design conversion technique, which can be easily merged into the electronic design automation (EDA) tool chain. We evaluate the effectiveness of our proposed design methodology considering various implementations of advanced encryption standard (AES) systems as case studies. We show that our proposed design methodology benefits from design automation with high security, and protection at the cost of low area, and power consumption overheads, when compared with traditional design methodologies.
secure test, intellectual property protection
0018-9529
1243 - 1253
Shafik, Rishad Ahmed
aa0bdafc-b022-4cb2-a8ef-4bf8a03ba524
Mathew, Jimson
156eec1e-d690-43eb-a72f-daefd8b04144
Pradhan, Dhiraj K.
14f13d30-42ec-43bf-941b-3116a7f803fc
Shafik, Rishad Ahmed
aa0bdafc-b022-4cb2-a8ef-4bf8a03ba524
Mathew, Jimson
156eec1e-d690-43eb-a72f-daefd8b04144
Pradhan, Dhiraj K.
14f13d30-42ec-43bf-941b-3116a7f803fc

Shafik, Rishad Ahmed, Mathew, Jimson and Pradhan, Dhiraj K. (2015) A unified design methodology for secure test and IP core protection. IEEE Transactions on Reliability, 64 (4), 1243 - 1253. (doi:10.1109/TR.2015.2464011).

Record type: Article

Abstract

On-chip security is an emerging challenge in the design of embedded systems with intellectual property (IP) cores. Traditionally this challenge is addressed using ad hoc design techniques with separate design objectives of secure design for testability (DfT), and IP core protection. However, in this paper, we will argue that such design approaches can incur high costs. Underpinning this argument, we propose a novel design methodology, called Secure TEst and IP core Protection (STEP), which aims to address the joint objective of IP core protection and secure testing. To ensure that this objective is achieved at a low cost, the STEP design methodology employs common key integrated hardware. This hardware is incorporated in the system through an automated design conversion technique, which can be easily merged into the electronic design automation (EDA) tool chain. We evaluate the effectiveness of our proposed design methodology considering various implementations of advanced encryption standard (AES) systems as case studies. We show that our proposed design methodology benefits from design automation with high security, and protection at the cost of low area, and power consumption overheads, when compared with traditional design methodologies.

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More information

Accepted/In Press date: June 2015
e-pub ahead of print date: 14 August 2015
Published date: December 2015
Keywords: secure test, intellectual property protection
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 371898
URI: http://eprints.soton.ac.uk/id/eprint/371898
ISSN: 0018-9529
PURE UUID: aeab6206-63c5-47b2-a3d4-e55b99755b80

Catalogue record

Date deposited: 21 Nov 2014 11:24
Last modified: 19 Aug 2019 16:33

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