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Sequence-aware watermark design for soft IP embedded processors

Sequence-aware watermark design for soft IP embedded processors
Sequence-aware watermark design for soft IP embedded processors
This paper describes a design approach for incorporating sequence-aware watermarks in soft IP embedded processors. The influence of watermark sequence parameters on detection, area and power overheads is examined, and consequently a sequence-aware method for incorporating sequence-aware watermarks in soft IP Embedded Processors is proposed. The intrinsic parameters of sequences, such as the activity factor and the overlapping factor are introduced, and their impact on correlation results is demonstrated. Measurement experimental results from FPGA and ASIC validate the design approach and demonstrate the resulting IP protection and subsequent costs for constrained embedded processors. Results presented in this paper show that the tradeoff occurs between the watermark robustness against third party IP attacks and hardware implementation costs. The analysis of this tradeoff is provided and an application
specific watermark implementation is proposed.
watermarking, IP protection, embedded processors, correlation power analysis
1063-8210
1-14
Kufel, Jedrzej
3773135d-b647-4925-a12a-9c6f3eb38a23
Wilson, Peter R.
8a65c092-c197-4f43-b8fc-e12977783cb3
Hill, Stephen
0f32be21-7776-4c8d-9cbc-57471f6f64ae
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Kufel, Jedrzej
3773135d-b647-4925-a12a-9c6f3eb38a23
Wilson, Peter R.
8a65c092-c197-4f43-b8fc-e12977783cb3
Hill, Stephen
0f32be21-7776-4c8d-9cbc-57471f6f64ae
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d

Kufel, Jedrzej, Wilson, Peter R., Hill, Stephen and Al-Hashimi, Bashir M. (2015) Sequence-aware watermark design for soft IP embedded processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Summer Issue, 1-14. (doi:10.1109/TVLSI.2015.2399457).

Record type: Article

Abstract

This paper describes a design approach for incorporating sequence-aware watermarks in soft IP embedded processors. The influence of watermark sequence parameters on detection, area and power overheads is examined, and consequently a sequence-aware method for incorporating sequence-aware watermarks in soft IP Embedded Processors is proposed. The intrinsic parameters of sequences, such as the activity factor and the overlapping factor are introduced, and their impact on correlation results is demonstrated. Measurement experimental results from FPGA and ASIC validate the design approach and demonstrate the resulting IP protection and subsequent costs for constrained embedded processors. Results presented in this paper show that the tradeoff occurs between the watermark robustness against third party IP attacks and hardware implementation costs. The analysis of this tradeoff is provided and an application
specific watermark implementation is proposed.

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Sequence-Aware Watermark Design for Soft IP Embedded Processors - final_authors_copy[2].pdf - Accepted Manuscript
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Sequence-Aware Watermark Design for Soft IP Embedded Processors - final.pdf - Accepted Manuscript
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More information

Accepted/In Press date: January 2015
e-pub ahead of print date: 20 March 2015
Published date: 20 March 2015
Keywords: watermarking, IP protection, embedded processors, correlation power analysis
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 373734
URI: https://eprints.soton.ac.uk/id/eprint/373734
ISSN: 1063-8210
PURE UUID: 2f82fb1c-9e42-4f7c-a8ee-19938021e397

Catalogue record

Date deposited: 27 Jan 2015 11:42
Last modified: 17 May 2018 16:32

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