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Performance evaluation of multi-core multi-cluster architecture (MCMCA)

Performance evaluation of multi-core multi-cluster architecture (MCMCA)
Performance evaluation of multi-core multi-cluster architecture (MCMCA)
A multi-core cluster is a cluster composed of numbers of nodes where each node has a number of processors, each with more than one core within each single chip. Cluster nodes are connected via an interconnection network. Multi-cored processors are able to achieve higher performance without driving up power consumption and heat, which is the main concern in a single-core processor. A general problem in the network arises from the fact that multiple messages can be in transit at the same time on the same network links. This chapter considers the communication latencies of a multi core multi cluster architecture, investigated using simulation experiments and measurements under various working conditions.
978-1466682108
IGI Global
Hamid, Norhazlina
22e1e955-20ef-4d80-92e3-1d2e8813f334
Walters, Robert J.
7b8732fb-3083-4f4d-844e-85a29daaa2c1
Wills, Gary B.
3a594558-6921-4e82-8098-38cd8d4e8aa0
Chang, Victor
Walters, Robert John
Wills, Gary
Hamid, Norhazlina
22e1e955-20ef-4d80-92e3-1d2e8813f334
Walters, Robert J.
7b8732fb-3083-4f4d-844e-85a29daaa2c1
Wills, Gary B.
3a594558-6921-4e82-8098-38cd8d4e8aa0
Chang, Victor
Walters, Robert John
Wills, Gary

Hamid, Norhazlina, Walters, Robert J. and Wills, Gary B. (2015) Performance evaluation of multi-core multi-cluster architecture (MCMCA). In, Chang, Victor, Walters, Robert John and Wills, Gary (eds.) Delivery and Adoption of Cloud Computing Services in Contemporary Organizations. Hershey, US. IGI Global.

Record type: Book Section

Abstract

A multi-core cluster is a cluster composed of numbers of nodes where each node has a number of processors, each with more than one core within each single chip. Cluster nodes are connected via an interconnection network. Multi-cored processors are able to achieve higher performance without driving up power consumption and heat, which is the main concern in a single-core processor. A general problem in the network arises from the fact that multiple messages can be in transit at the same time on the same network links. This chapter considers the communication latencies of a multi core multi cluster architecture, investigated using simulation experiments and measurements under various working conditions.

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More information

Published date: 31 March 2015
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 374908
URI: http://eprints.soton.ac.uk/id/eprint/374908
ISBN: 978-1466682108
PURE UUID: c65f6252-fdf2-438f-8682-02e533133660
ORCID for Gary B. Wills: ORCID iD orcid.org/0000-0001-5771-4088

Catalogue record

Date deposited: 06 Mar 2015 09:09
Last modified: 09 Nov 2021 02:51

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Contributors

Author: Norhazlina Hamid
Author: Robert J. Walters
Author: Gary B. Wills ORCID iD
Editor: Victor Chang
Editor: Robert John Walters
Editor: Gary Wills

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