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Autonomous soft-error tolerance of FPGA configuration bits

Autonomous soft-error tolerance of FPGA configuration bits
Autonomous soft-error tolerance of FPGA configuration bits
Field-programmable gate arrays (FPGAs) are increasingly susceptible to radiation-induced single event upsets (SEUs). These upsets are predominant in a space environment; however, with increasing use of static RAM (SRAM) in modern FPGAs, these SEUs are gaining prominence even in a terrestrial environment. SEUs can flip SRAM bits of FPGA, potentially altering the functionality of the implemented design. This has motivated FPGA designers to investigate techniques to protect the FPGA configuration bits against such inadvertent bit flips (soft error). Traditionally, triple modular redundancy (TMR) is used to protect the FPGA bit flips. Increasing design complexity and limited battery life motivate for alternative approaches for soft-error tolerance. In this article, we propose a technique to improve autonomous fault-masking capabilities of a design by maximizing the number of zeros or ones in lookup tables (LUTs). The technique analyzes critical configuration bits and utilizes spare resources (XOR gates and carry chains) of FPGAs to selectively manipulate the logic implemented in LUTs using two operations: LUT restructuring and LUT decomposition. We implemented the proposed approach for Xilinx Virtex-6 FPGAs and validated the same with a wide set of designs from the MCNC, IWLS 2005, and ITC99 benchmark suites. Results demonstrate that the proposed logic restructuring maximizes logic 0 (or 1) of LUTs by an average of 20%, achieving 80% fault masking with no area overhead. The fault rate of the entire design is reduced by 60% on average as compared to the existing techniques. Furthermore, the logic decomposition algorithm provides incremental fault-tolerance capabilities and achieves an additional 5% fault masking with an average 7% increase in slice usage.

The complete methodology is implemented into a tool for Xilinx FPGA and is made available online for the benefit of the research community. The algorithms are lightweight, and the whole design flow (including Xilinx Place and Route) was completed in 75 minutes for the largest benchmark in the set.
fpgas, soft errors, sram configuration bits, luts
1936-7406
12-[17pp]
Das, Anup K.
2a0d6cea-309b-4053-a62e-234807f89306
Venkataraman, Shyamsundar
98224454-4ef8-44aa-bc25-33d7e15a7959
Kumar, Akash
3e1191e9-dc51-4f9e-8e47-80524db219dc
Das, Anup K.
2a0d6cea-309b-4053-a62e-234807f89306
Venkataraman, Shyamsundar
98224454-4ef8-44aa-bc25-33d7e15a7959
Kumar, Akash
3e1191e9-dc51-4f9e-8e47-80524db219dc

Das, Anup K., Venkataraman, Shyamsundar and Kumar, Akash (2015) Autonomous soft-error tolerance of FPGA configuration bits. ACM Transactions on Reconfigurable Technology and Systems, 8 (2), 12-[17pp]. (doi:10.1145/2629580).

Record type: Article

Abstract

Field-programmable gate arrays (FPGAs) are increasingly susceptible to radiation-induced single event upsets (SEUs). These upsets are predominant in a space environment; however, with increasing use of static RAM (SRAM) in modern FPGAs, these SEUs are gaining prominence even in a terrestrial environment. SEUs can flip SRAM bits of FPGA, potentially altering the functionality of the implemented design. This has motivated FPGA designers to investigate techniques to protect the FPGA configuration bits against such inadvertent bit flips (soft error). Traditionally, triple modular redundancy (TMR) is used to protect the FPGA bit flips. Increasing design complexity and limited battery life motivate for alternative approaches for soft-error tolerance. In this article, we propose a technique to improve autonomous fault-masking capabilities of a design by maximizing the number of zeros or ones in lookup tables (LUTs). The technique analyzes critical configuration bits and utilizes spare resources (XOR gates and carry chains) of FPGAs to selectively manipulate the logic implemented in LUTs using two operations: LUT restructuring and LUT decomposition. We implemented the proposed approach for Xilinx Virtex-6 FPGAs and validated the same with a wide set of designs from the MCNC, IWLS 2005, and ITC99 benchmark suites. Results demonstrate that the proposed logic restructuring maximizes logic 0 (or 1) of LUTs by an average of 20%, achieving 80% fault masking with no area overhead. The fault rate of the entire design is reduced by 60% on average as compared to the existing techniques. Furthermore, the logic decomposition algorithm provides incremental fault-tolerance capabilities and achieves an additional 5% fault masking with an average 7% increase in slice usage.

The complete methodology is implemented into a tool for Xilinx FPGA and is made available online for the benefit of the research community. The algorithms are lightweight, and the whole design flow (including Xilinx Place and Route) was completed in 75 minutes for the largest benchmark in the set.

Full text not available from this repository.

More information

Published date: March 2015
Keywords: fpgas, soft errors, sram configuration bits, luts
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 376437
URI: https://eprints.soton.ac.uk/id/eprint/376437
ISSN: 1936-7406
PURE UUID: bbb1518f-a3a2-41a0-af90-09eadf3e2a9e

Catalogue record

Date deposited: 28 Apr 2015 12:57
Last modified: 17 Jul 2017 21:09

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