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Communication and migration energy aware task mapping for reliable multiprocessor systems

Communication and migration energy aware task mapping for reliable multiprocessor systems
Communication and migration energy aware task mapping for reliable multiprocessor systems
Heterogeneous multiprocessor systems-on-chip (MPSoCs) are emerging as a promising solution in deep sub-micron technology nodes to satisfy design performance and power requirements. However, shrinking transistor geometry and aggressive voltage scaling are negatively impacting the dependability of these MPSoCs by increasing the chances of failures. This paper proposes an offline (design-time) task remapping technique to minimize the communication energy and task migration overhead of an application mapped on a heterogeneous multiprocessor system for all processor fault-scenarios. The proposed technique involves two steps–(1) Communication Energy driven Design Space Exploration (CDSE) to select an initial mapping and (2) Communication energy and Migration overhead aware Task Mapping (CMTM) for different fault-scenarios. The CDSE is formulated as a Mixed Integer Quadratic Programming (MIQP) problem and solved using an energy-gradient based heuristic. The CMTM problem is solved using a fast heuristic with the starting mapping selected using CDSE step. The proposed two steps technique is compared with state-of-the-art approaches through rigorous simulations with synthetic and real application graphs. Results demonstrate that the proposed CDSE reduces design space exploration time by 99% with a maximum variation of 5% from the optimal solution obtained by solving the MIQP problem directly. Further, the proposed CMTM reduces communication energy by an average 35% and migration overhead by an average 20% for all single and double fault-scenarios as compared to the existing fault-tolerant techniques. The CMTM also achieves over 30x reductions in execution time for large problem sizes with a maximum deviation of 15% from the minimum communication energy achievable with the given application on a given architecture. For streaming multimedia applications, the proposed technique delivers 50% higher throughput per unit energy as compared to the existing approaches.
fault-tolerance, heterogeneous mpsocs, design space exploration, task mapping, mixed integer quadratic programming
216-228
Das, Anup K.
2a0d6cea-309b-4053-a62e-234807f89306
Kumar, Akash
3e1191e9-dc51-4f9e-8e47-80524db219dc
Veeravalli, Bharadwaj
b836c94d-baad-450a-826b-84021f56db49
Das, Anup K.
2a0d6cea-309b-4053-a62e-234807f89306
Kumar, Akash
3e1191e9-dc51-4f9e-8e47-80524db219dc
Veeravalli, Bharadwaj
b836c94d-baad-450a-826b-84021f56db49

Das, Anup K., Kumar, Akash and Veeravalli, Bharadwaj (2014) Communication and migration energy aware task mapping for reliable multiprocessor systems. [in special issue: Extreme Scale Parallel Architectures and Systems, Cryptography in Cloud Computing and Recent Advances in Parallel and Distributed Systems, ICPADS 2012 Selected Papers] Future Generation Computer Systems, 30, 216-228. (doi:10.1016/j.future.2013.06.016).

Record type: Article

Abstract

Heterogeneous multiprocessor systems-on-chip (MPSoCs) are emerging as a promising solution in deep sub-micron technology nodes to satisfy design performance and power requirements. However, shrinking transistor geometry and aggressive voltage scaling are negatively impacting the dependability of these MPSoCs by increasing the chances of failures. This paper proposes an offline (design-time) task remapping technique to minimize the communication energy and task migration overhead of an application mapped on a heterogeneous multiprocessor system for all processor fault-scenarios. The proposed technique involves two steps–(1) Communication Energy driven Design Space Exploration (CDSE) to select an initial mapping and (2) Communication energy and Migration overhead aware Task Mapping (CMTM) for different fault-scenarios. The CDSE is formulated as a Mixed Integer Quadratic Programming (MIQP) problem and solved using an energy-gradient based heuristic. The CMTM problem is solved using a fast heuristic with the starting mapping selected using CDSE step. The proposed two steps technique is compared with state-of-the-art approaches through rigorous simulations with synthetic and real application graphs. Results demonstrate that the proposed CDSE reduces design space exploration time by 99% with a maximum variation of 5% from the optimal solution obtained by solving the MIQP problem directly. Further, the proposed CMTM reduces communication energy by an average 35% and migration overhead by an average 20% for all single and double fault-scenarios as compared to the existing fault-tolerant techniques. The CMTM also achieves over 30x reductions in execution time for large problem sizes with a maximum deviation of 15% from the minimum communication energy achievable with the given application on a given architecture. For streaming multimedia applications, the proposed technique delivers 50% higher throughput per unit energy as compared to the existing approaches.

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More information

Accepted/In Press date: 17 June 2013
e-pub ahead of print date: 26 June 2013
Published date: January 2014
Keywords: fault-tolerance, heterogeneous mpsocs, design space exploration, task mapping, mixed integer quadratic programming
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 376438
URI: https://eprints.soton.ac.uk/id/eprint/376438
PURE UUID: a87440dc-346c-4763-b785-a12e33285bce

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Date deposited: 28 Apr 2015 13:13
Last modified: 15 Jul 2019 21:22

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Contributors

Author: Anup K. Das
Author: Akash Kumar
Author: Bharadwaj Veeravalli

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