Defect aware X-filling for low-power scan testing
Defect aware X-filling for low-power scan testing
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads to lower defect coverage than random-fill. We propose a unified low-power and defect-aware X-filling method for scan testing. The proposed method reduces shift power under constraints on the peak power during response capture, and the power reduction is comparable to that for the Fill-Adjacent X-filling method. At the same time, this approach provides high defect coverage, which approaches and in many cases is higher than that for random-fill, without increasing the pattern count. The advantages of the proposed method are demonstrated with simulation results for the largest ISCAS and the IWLS benchmark circuits
Balatsouka, S.
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Tenentes, Vasileios
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Kavousianos, X.
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Chakrabarty, K.
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Balatsouka, S.
084f2949-f84a-4ee4-ab21-d278bfd8fde8
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Kavousianos, X.
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Chakrabarty, K.
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Balatsouka, S., Tenentes, Vasileios, Kavousianos, X. and Chakrabarty, K.
(2010)
Defect aware X-filling for low-power scan testing.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, Dresden, Germany.
08 - 12 Mar 2010.
6 pp
.
(doi:10.1109/DATE.2010.5456928).
Record type:
Conference or Workshop Item
(Paper)
Abstract
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads to lower defect coverage than random-fill. We propose a unified low-power and defect-aware X-filling method for scan testing. The proposed method reduces shift power under constraints on the peak power during response capture, and the power reduction is comparable to that for the Fill-Adjacent X-filling method. At the same time, this approach provides high defect coverage, which approaches and in many cases is higher than that for random-fill, without increasing the pattern count. The advantages of the proposed method are demonstrated with simulation results for the largest ISCAS and the IWLS benchmark circuits
Text
Balatsouka_DATE2010.pdf
- Accepted Manuscript
More information
e-pub ahead of print date: 11 February 2010
Venue - Dates:
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, Dresden, Germany, 2010-03-08 - 2010-03-12
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 377311
URI: http://eprints.soton.ac.uk/id/eprint/377311
PURE UUID: e12da15a-eeb9-4f0d-bbd2-b183a5fdd7b5
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Date deposited: 29 May 2015 08:58
Last modified: 14 Mar 2024 20:00
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Contributors
Author:
S. Balatsouka
Author:
Vasileios Tenentes
Author:
X. Kavousianos
Author:
K. Chakrabarty
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