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Area Efficient Configurable Physical Unclonable Functions for FPGAs Identification

Area Efficient Configurable Physical Unclonable Functions for FPGAs Identification
Area Efficient Configurable Physical Unclonable Functions for FPGAs Identification
Physical Unclonable Functions (PUF) is an emerging design technology for secure hardware. It exploits the
physical manufacturing variations of silicon ICs to generate a unique signature for each chip. A Ring Oscillator (RO) based PUF is a promising solution for the authentication of FPGA devices. However; this technique has not yet been widely adopted
due to its large area costs and the lack of platform-independent PUF architectures which are “easy to implement”. Existing RO
PUF design requires large number of ring oscillators to generate a relatively safe unique identifier; they also have complex routing requirements. This work proposes a novel configurable RO PUF architecture easily portable between different FPGA platforms.
It also offers significantly larger number of challenge-response
pairs compared to existing solutions with the same area
overheads. The design was realized and characterized using an
Altera FPGA device. Experimental results show that the quality of this design conforms to the requirements of general RO PUF.
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Hu, Yizhong Hu
9ea78339-13a7-4617-bcb0-adf049acf6b7
Mispan, Mohd Syafiq
1213c616-83bc-4223-8de3-72e259d62cce
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Hu, Yizhong Hu
9ea78339-13a7-4617-bcb0-adf049acf6b7
Mispan, Mohd Syafiq
1213c616-83bc-4223-8de3-72e259d62cce

Halak, Basel, Hu, Yizhong Hu and Mispan, Mohd Syafiq (2015) Area Efficient Configurable Physical Unclonable Functions for FPGAs Identification At IEEE International Symposium on Circuits and Systems (ISCAS), Portugal. 24 - 27 May 2015.

Record type: Conference or Workshop Item (Paper)

Abstract

Physical Unclonable Functions (PUF) is an emerging design technology for secure hardware. It exploits the
physical manufacturing variations of silicon ICs to generate a unique signature for each chip. A Ring Oscillator (RO) based PUF is a promising solution for the authentication of FPGA devices. However; this technique has not yet been widely adopted
due to its large area costs and the lack of platform-independent PUF architectures which are “easy to implement”. Existing RO
PUF design requires large number of ring oscillators to generate a relatively safe unique identifier; they also have complex routing requirements. This work proposes a novel configurable RO PUF architecture easily portable between different FPGA platforms.
It also offers significantly larger number of challenge-response
pairs compared to existing solutions with the same area
overheads. The design was realized and characterized using an
Altera FPGA device. Experimental results show that the quality of this design conforms to the requirements of general RO PUF.

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More information

Published date: 24 May 2015
Venue - Dates: IEEE International Symposium on Circuits and Systems (ISCAS), Portugal, 2015-05-24 - 2015-05-27
Organisations: EEE

Identifiers

Local EPrints ID: 379685
URI: http://eprints.soton.ac.uk/id/eprint/379685
PURE UUID: db29b0ee-9be6-4525-9fad-0410430c369d

Catalogue record

Date deposited: 27 Jul 2015 12:43
Last modified: 17 Jul 2017 20:41

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Contributors

Author: Basel Halak
Author: Yizhong Hu Hu
Author: Mohd Syafiq Mispan

University divisions

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