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Modeling and tools for power supply variations analysis in networks-on-chip

Modeling and tools for power supply variations analysis in networks-on-chip
Modeling and tools for power supply variations analysis in networks-on-chip
Power supply integrity has become a critical concern with the rapid shrinking feature size and the ever increasing power consumption in nanometre scale integration. In particular, on-chip communication in platforms such as networks-on-chip (NoC) dictates the power dissipation and overall system performance in multicore systems and embedded computing architectures. These architectures require a dedicated tool for analyzing the power supply noise which must embed distinctive communication characteristics and spatial parameters. In this paper, we present a tool dedicated to determining the on-chip VDD drops due to communication workload in NoCs. This tool integrates a fast power grid model, an NoC simulator, an on-chip link model, and a microarchitectural power model for router. The model has been rigorously verified using SPICE simulations. The proposed model and tools are further exemplified through analyzing the impact of power supply noise for NoC links. Statistical timing analysis of NoC links in the presence of power supply noise was performed to evaluate the bit error rates (BERs). This work would enable better understanding of the tradeoffs existing in the design of NoCs, and the induced power supply noise due to on-chip communication. This understanding is crucial for the analysis of the quality of service (QoS) of communication fabrics in NoCs at the early design stages.
networks-on-chip, power supply noise, power grid simulations, on-chip routing, timing analysis, power grid granularity, probability of error, bit error rate
679-690
Dehir, Nizar
28124aff-d3c5-40cb-86ac-b2088f8418aa
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53
Fei, Xia
d72742d7-72ef-4358-8490-5db564208d31
Alex, Yakovlev
07fb9854-641d-4836-ab30-1907f0eb9b00
Dehir, Nizar
28124aff-d3c5-40cb-86ac-b2088f8418aa
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53
Fei, Xia
d72742d7-72ef-4358-8490-5db564208d31
Alex, Yakovlev
07fb9854-641d-4836-ab30-1907f0eb9b00

Dehir, Nizar, Mak, Terrence, Fei, Xia and Alex, Yakovlev (2014) Modeling and tools for power supply variations analysis in networks-on-chip. IEEE Transactions on Computers, 63 (3), 679-690. (doi:10.1109/TC.2012.272).

Record type: Article

Abstract

Power supply integrity has become a critical concern with the rapid shrinking feature size and the ever increasing power consumption in nanometre scale integration. In particular, on-chip communication in platforms such as networks-on-chip (NoC) dictates the power dissipation and overall system performance in multicore systems and embedded computing architectures. These architectures require a dedicated tool for analyzing the power supply noise which must embed distinctive communication characteristics and spatial parameters. In this paper, we present a tool dedicated to determining the on-chip VDD drops due to communication workload in NoCs. This tool integrates a fast power grid model, an NoC simulator, an on-chip link model, and a microarchitectural power model for router. The model has been rigorously verified using SPICE simulations. The proposed model and tools are further exemplified through analyzing the impact of power supply noise for NoC links. Statistical timing analysis of NoC links in the presence of power supply noise was performed to evaluate the bit error rates (BERs). This work would enable better understanding of the tradeoffs existing in the design of NoCs, and the induced power supply noise due to on-chip communication. This understanding is crucial for the analysis of the quality of service (QoS) of communication fabrics in NoCs at the early design stages.

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TCSI-2011-10-0782.R1_Dahir.pdf - Accepted Manuscript
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More information

Accepted/In Press date: 1 November 2012
e-pub ahead of print date: 20 November 2012
Published date: March 2014
Keywords: networks-on-chip, power supply noise, power grid simulations, on-chip routing, timing analysis, power grid granularity, probability of error, bit error rate
Organisations: Faculty of Engineering and the Environment

Identifiers

Local EPrints ID: 383047
URI: http://eprints.soton.ac.uk/id/eprint/383047
PURE UUID: 9196a86c-dccf-4791-9103-64e8e8fd233d

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Date deposited: 05 Nov 2015 12:04
Last modified: 28 Oct 2019 20:39

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Contributors

Author: Nizar Dehir
Author: Terrence Mak
Author: Xia Fei
Author: Yakovlev Alex

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