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Eliminating synchronization latency using sequenced latching

Eliminating synchronization latency using sequenced latching
Eliminating synchronization latency using sequenced latching
Modern multicore systems have a large number of components operating in different clock domains and communicating through asynchronous interfaces. These interfaces use synchronizer circuits, which guard against metastability failures but introduce latency in processing the asynchronous input. We propose a speculative method that hides synchronization latency by overlapping it with computation cycles. We verify the correctness of our approach through a field programmable gate array implementation and apply it to a number of synthesized benchmarks. Synthesis results reveal that our approach achieves average savings of 135% and 204% in area costs and nearly 100% in power costs compared to two similar speculative techniques
duplication, latency, metastability, speculation, synchronization
1063-8210
408-419
Tarawneh, Gareth
ebfcb623-06f7-411d-83b7-df8e91a8ca7a
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53
Tarawneh, Gareth
ebfcb623-06f7-411d-83b7-df8e91a8ca7a
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53

Tarawneh, Gareth, Yakovlev, Alex and Mak, Terrence (2014) Eliminating synchronization latency using sequenced latching. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22 (2), 408-419. (doi:10.1109/TVLSI.2013.2243177).

Record type: Article

Abstract

Modern multicore systems have a large number of components operating in different clock domains and communicating through asynchronous interfaces. These interfaces use synchronizer circuits, which guard against metastability failures but introduce latency in processing the asynchronous input. We propose a speculative method that hides synchronization latency by overlapping it with computation cycles. We verify the correctness of our approach through a field programmable gate array implementation and apply it to a number of synthesized benchmarks. Synthesis results reveal that our approach achieves average savings of 135% and 204% in area costs and nearly 100% in power costs compared to two similar speculative techniques

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More information

Accepted/In Press date: 30 December 2012
e-pub ahead of print date: 12 February 2013
Published date: February 2014
Keywords: duplication, latency, metastability, speculation, synchronization
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 383050
URI: https://eprints.soton.ac.uk/id/eprint/383050
ISSN: 1063-8210
PURE UUID: a2062ea0-d46d-44c6-b6b5-8359cd0deff7

Catalogue record

Date deposited: 05 Nov 2015 12:50
Last modified: 15 Jul 2019 21:00

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Contributors

Author: Gareth Tarawneh
Author: Alex Yakovlev
Author: Terrence Mak

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