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Ageing Impact on a High Speed Voltage Comparator with Hysteresis

Nawi, Illani, Halak, Basel and Zwolinski, Mark (2016) Ageing Impact on a High Speed Voltage Comparator with Hysteresis At Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems.

Record type: Conference or Workshop Item (Poster)

Abstract

Impact of aging on single event transients in a high speed
comparator-with-hysteresis in 65-nm CMOS technology using
SPICE simulations is investigated. The most sensitive transistor
identified from sensitivity analysis was irradiated under both
aging-free and under aging, running at maximum parameter
drift of 10% on all PMOS transistors for 10 stress years and
later analyzed for its synergism between NBTI and single event
transients. NBTI does not significantly affect the single event
transients vulnerability of the comparator, at all hysteresis voltage
ranging from 0 to 64.4 mV for 10 MHz and 1 GHz input
frequencies.

Full text not available from this repository.

More information

Published date: 2016
Venue - Dates: Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016-03-18
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 385874
URI: http://eprints.soton.ac.uk/id/eprint/385874
PURE UUID: fc202f9e-27da-4bfc-b176-13cff996b257
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 13 Jan 2016 17:06
Last modified: 17 Jul 2017 19:53

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Contributors

Author: Illani Nawi
Author: Basel Halak
Author: Mark Zwolinski ORCID iD

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