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Static Aging Analysis Using 3-Dimensional Delay Library

Haider, Abbas, Halak, Basel and Zwolinsk, Mark (2016) Static Aging Analysis Using 3-Dimensional Delay Library At Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems.

Record type: Conference or Workshop Item (Poster)

Abstract

The growing concern about time-dependent performance
variations of CMOS devices due to aging-induced delay
degradation has increased with shrinking technology dimensions
of the devices . One of the main causes of aging is Negative Bias
Temperature Instability (NBTI). Modeling NBTI-induced delay
at gate level depends on the real stress activity of gate inputs
which are related to the workload applied from the higher level
of abstraction (e.g. Application). Having estimated values about
the degradation delays can make design stage to consider this
issue as a design constrain and even to precisely allocate the
online aging sensors. this paper propose a method to include the
stress probability within technology library as three dimensional
look-up tables for Static Timing Analysis(STA) process of the
design as an approach named Static Aging Analysis(SAA). the
purpose of this approach is instead of estimating only the timing
delay at time zero, estimating NBTI-induced delays for predefined
lifetime of the product.

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More information

Published date: 18 March 2016
Venue - Dates: Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016-03-18
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 385876
URI: http://eprints.soton.ac.uk/id/eprint/385876
PURE UUID: a9a1266a-02e1-41be-98a0-9db45d47336b
ORCID for Mark Zwolinsk: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 13 Jan 2016 17:13
Last modified: 17 Jul 2017 19:53

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Contributors

Author: Abbas Haider
Author: Basel Halak
Author: Mark Zwolinsk ORCID iD

University divisions

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