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NBTI Lifetime Evaluation and Extension in Instruction Caches

Shengyu, Duan, Halak, Basel, Zwolinski, Mark and Wong, Rick (2016) NBTI Lifetime Evaluation and Extension in Instruction Caches At Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems.

Record type: Conference or Workshop Item (Poster)


CMOS devices suffer from wearout mechanisms
resulting in reliability issues. Negative bias temperature instability
(NBTI) is one of the dominant ageing effects that can
cause threshold voltage shift on PMOS devices and subsequently
impact circuit performance. The static noise margin (SNM) of an
SRAM cell may be sharply reduced with unbalanced NBTI stress.
This will impact SRAM read stability. From our observations
of instruction caches, NBTI stress duty cycles for each cache
line generally have similar but unbalanced patterns even when
running very different programs. Based on the patterns, we
propose an algorithm to evaluate the lifetime of instruction
caches by running SPICE simulation. The results predict 6
and 7 years NBTI lifetimes of instruction caches for ARM and
MIPS architectures respectively. One of the practical solutions
is periodically flipping each cell to balance the degradation rate.
However the performance benefits in terms of lifetime are not
actually proven before. Using the stress patterns and lifetime
evaluation algorithm, our work for the first time prove this
technique can extend the lifetime of the cache by two orders
of magnitude.

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Published date: 2016
Venue - Dates: Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016-03-18
Organisations: Electronics & Computer Science


Local EPrints ID: 385878
PURE UUID: b3a0cc33-d7d8-42be-9642-619aea13d19a

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Date deposited: 13 Jan 2016 17:22
Last modified: 17 Jul 2017 19:53

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Author: Duan Shengyu
Author: Basel Halak
Author: Mark Zwolinski
Author: Rick Wong

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