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VLSI implementation of fully-parallel LTE turbo decoders

Li, An, Xiang, Luping, Chen, Taihai, Maunder, Robert G., Al-Hashimi, Bashir M. and Hanzo, Lajos (2016) VLSI implementation of fully-parallel LTE turbo decoders IEEE Access, 3, pp. 1-24. (doi:10.1109/ACCESS.2016.2515719).

Record type: Article


Turbo codes facilitate near-capacity transmission throughputs by achieving a reliable iterative forward error correction. However, owing to the serial data dependence imposed by the logarithmic Bahl–Cocke–Jelinek–Raviv algorithm, the limited processing throughputs of the conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time communication schemes. Motivated by this, we recently proposed a floating-point fully parallel turbo decoder (FPTD) algorithm, which eliminates the serial data dependence, allowing parallel processing and hence significantly reducing the number of clock cycles required. In this paper, we conceive a technique for reducing the critical datapath of the FPTD, and we propose a novel fixed-point version as well as its very large scale integration (VLSI) implementation. We also propose a novel technique, which allows the FPTD to also decode shorter frames employing compatible interleaver patterns. We strike beneficial tradeoffs amongst the latency, core area, and energy consumption by investigating the minimum bit widths and techniques for message log-likelihood ratio scaling and state metric normalization. Accordingly, the design flow and design tradeoffs considered in this paper are also applicable to other fixed-point implementations of error correction decoders. We demonstrate that upon using Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm low-power technology for decoding the longest long-term evolution frames (6144 b) received over an additive white Gaussian noise channel having Eb/N0 = 1 dB, the proposed fixed-point FPTD VLSI achieves a processing throughput of 21.9 Gb/s and a processing latency of 0.28 ?s. These results are 17.1 times superior to those of the state-of-the-art benchmarker. Furthermore, the proposed fixed-point FPTD VLSI achieves an energy consumption of 2.69 ?J/frame and a normalized core area of 5 mm2/Gb/s, which are 34% and 23% lower than those of the benchmarker, respectively.

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Accepted/In Press date: 5 January 2016
Published date: 11 January 2016
Organisations: Electronic & Software Systems, Southampton Wireless Group


Local EPrints ID: 386016
PURE UUID: 72446e6a-9fe7-4ce7-bd51-0a17b5e5f902
ORCID for Robert G. Maunder: ORCID iD

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Date deposited: 16 Jan 2016 03:37
Last modified: 17 Jul 2017 19:52

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Author: An Li
Author: Luping Xiang
Author: Taihai Chen
Author: Robert G. Maunder ORCID iD
Author: Lajos Hanzo

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