Sazio, P.J.A., Berg, J., See, P., Ford, C.J.B., Lundgren, P., Greenham, N.C., Ginger, D.S., Bengtsson, S. and Chin, S.N.
A silicon structure for electrical characterisation of nanoscale elements
At 2001 MRS Spring Meeting.
16 - 20 Apr 2001.
Full text not available from this repository.
The problem of mass manufacturing electrode structures suitable for contacting nanoscale elements lies primarily in the difficulty of fabricating a nanometre-scale gap between two electrodes in a well controlled, highly parallel manner. In ULSI circuit production, the gate and substrate in MOSFETs are routinely fabricated with a precise vertical spacing of 3 nm between them.
In this work, we have investigated a number of highly parallel methods for the generation of nanogaps, including reconfiguration of the ubiquitous MOS device structure. The silicon dioxide layer that provides vertical separation and electrical insulation between two regions of silicon (the crystalline substrate and the poly-crystalline gate) gives a leakage current of 1 nA µm. In the future this kind of device has the potential to provide a bolt-on technology for the fabrication of ULSI circuits in which conventional CMOS devices are directly hybridised with functional nanoscale elements.
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