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Aging benefits in nanometer CMOS designs

Aging benefits in nanometer CMOS designs
Aging benefits in nanometer CMOS designs
In this paper, we show that BTI aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show static power reduction of 50% after only 1 month of operation, which exceeds 78% in 10 years. BTI aging beneficial effect on power consumption is also proved with experimental measurements.
1549-7747
324-328
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Yang, Sheng
04b9848f-ddd4-4d8f-93b6-b91a2144d49c
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Yang, Sheng
04b9848f-ddd4-4d8f-93b6-b91a2144d49c
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d

Rossi, Daniele, Tenentes, Vasileios, Yang, Sheng, Khursheed, Saqib and Al-Hashimi, Bashir (2017) Aging benefits in nanometer CMOS designs. IEEE Transactions on Circuits and Systems II: Express Briefs, 64 (3), 324-328. (doi:10.1109/TCSII.2016.2561206).

Record type: Article

Abstract

In this paper, we show that BTI aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show static power reduction of 50% after only 1 month of operation, which exceeds 78% in 10 years. BTI aging beneficial effect on power consumption is also proved with experimental measurements.

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Accepted/In Press date: 24 April 2016
e-pub ahead of print date: 2 May 2016
Published date: March 2017
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 393452
URI: https://eprints.soton.ac.uk/id/eprint/393452
ISSN: 1549-7747
PURE UUID: d3cedb46-4ac8-48d9-8279-62a556db65af

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Date deposited: 27 Apr 2016 10:38
Last modified: 10 Dec 2019 06:33

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Contributors

Author: Daniele Rossi
Author: Vasileios Tenentes
Author: Sheng Yang
Author: Saqib Khursheed
Author: Bashir Al-Hashimi

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