Aging benefits in nanometer CMOS designs

Abstract

In this paper, we show that BTI aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show static power reduction of 50% after only 1 month of operation, which exceeds 78% in 10 years. BTI aging beneficial effect on power consumption is also proved with experimental measurements.

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