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Modified micropipline architecture for synthesizable synchronous FIR filter design

Modified micropipline architecture for synthesizable synchronous FIR filter design
Modified micropipline architecture for synthesizable synchronous FIR filter design
The use of asynchronous design approaches to construct digital signal processing (DSP) systems is a rapidly growing research area driven by a wide range of emerging energy constrained applications such as wireless sensor network, portable medical devices and brain implants. The asynchronous design techniques allow the construction of systems which are samples driven, which means they only dissipate dynamic energy when there processing data and idle otherwise. This inherent advantage of asynchronous design over conventional synchronous circuits allows them to be energy efficient. However the implementation flow of asynchronous systems is still difficult due to its lack of compatibility with industry-standard synchronous design tools and modelling languages. This paper devises a novel asynchronous design for a finite impulse response (FIR) filter, an essential building block of DSP systems, which is synthesizable and suitable for implementation using conventional synchronous systems design flow and tools. The proposed design is based on a modified version of the micropipline architecture and it is constructed using four phase bundled data protocol. A hardware prototype of the proposed filter has been developed on an FPGA, and systematically verified. The results prove correct functionality of the novel design and a superior performance compared to a synchronous FIR implementation. The findings of this work will allow a wider adoption of asynchronous circuits by DSP designers to harness their energy and performance benefits.
0976-1527
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Chiu, Hsien-Chih
8c7bcaf1-dd98-4501-92e3-fc46147c5721
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Chiu, Hsien-Chih
8c7bcaf1-dd98-4501-92e3-fc46147c5721

Halak, Basel and Chiu, Hsien-Chih (2016) Modified micropipline architecture for synthesizable synchronous FIR filter design International Journal of VLSI Design & Communication Systems, Spring Issue

Record type: Article

Abstract

The use of asynchronous design approaches to construct digital signal processing (DSP) systems is a rapidly growing research area driven by a wide range of emerging energy constrained applications such as wireless sensor network, portable medical devices and brain implants. The asynchronous design techniques allow the construction of systems which are samples driven, which means they only dissipate dynamic energy when there processing data and idle otherwise. This inherent advantage of asynchronous design over conventional synchronous circuits allows them to be energy efficient. However the implementation flow of asynchronous systems is still difficult due to its lack of compatibility with industry-standard synchronous design tools and modelling languages. This paper devises a novel asynchronous design for a finite impulse response (FIR) filter, an essential building block of DSP systems, which is synthesizable and suitable for implementation using conventional synchronous systems design flow and tools. The proposed design is based on a modified version of the micropipline architecture and it is constructed using four phase bundled data protocol. A hardware prototype of the proposed filter has been developed on an FPGA, and systematically verified. The results prove correct functionality of the novel design and a superior performance compared to a synchronous FIR implementation. The findings of this work will allow a wider adoption of asynchronous circuits by DSP designers to harness their energy and performance benefits.

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More information

Published date: 15 March 2016
Organisations: Faculty of Physical Sciences and Engineering

Identifiers

Local EPrints ID: 394521
URI: http://eprints.soton.ac.uk/id/eprint/394521
ISSN: 0976-1527
PURE UUID: a3ff061c-047c-4422-8ad1-a2db307cf958

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Date deposited: 17 May 2016 16:48
Last modified: 27 Oct 2017 08:02

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Contributors

Author: Basel Halak
Author: Hsien-Chih Chiu

University divisions

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