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Analysis of BTI aging of level shifters

Halak, Basel, Rossi, Daniele and Jiajing, Cai (2016) Analysis of BTI aging of level shifters At 22nd IEEE International Symposium on On-Line Testing and Robust System Design.

Record type: Conference or Workshop Item (Paper)


This paper provides a comprehensive evaluation of the effects of Bias Temperature Instability (BTI) aging on the delay and power consumption of level shifters. The latter are indispensable blocks in energy efficient systems with multiple supply voltages. Our results show that conventional level-up shifters exhibit significantly more delay and power aging-related degradation compared to standard logic cells. Our experiments performed in a predictive 32 nm technology indicate those designs can suffer from more than 200% increase in their delay after 5 years due to BTI aging compared to an average of 20% delay rise in the case of standard CMOS logic. A similar trend has also been observed when evaluating the increases in power consumption due to aging. Our investigations show that the reason behind this phenomenon is the differential signaling structure present in the majority of conventional level up shifters, combined with the use of low supply voltages.

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Accepted/In Press date: 3 May 2016
Venue - Dates: 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016-05-03
Organisations: Faculty of Physical Sciences and Engineering


Local EPrints ID: 394546
PURE UUID: bb14da87-0ab3-414f-9be3-7246b588c081

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Date deposited: 17 May 2016 17:03
Last modified: 17 Jul 2017 19:00

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Author: Basel Halak
Author: Daniele Rossi
Author: Cai Jiajing

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