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Susceptible workload driven selective fault tolerance using a probabilistic fault model

Susceptible workload driven selective fault tolerance using a probabilistic fault model
Susceptible workload driven selective fault tolerance using a probabilistic fault model
In this paper, we present a novel fault tolerance design technique, which is applicable at the register transfer level, based on protecting the functionality of logic circuits using a probabilistic fault model. The proposed technique selects the most susceptible workload of combinational circuits to protect against probabilistic faults. The workload susceptibility is ranked as the likelihood of any fault to bypass the inherent logical masking of the circuit and propagate an erroneous response to its outputs, when that workload is executed. The workload protection is achieved through a Triple Modular Redundancy (TMR) scheme by using the patterns that have been evaluated as most susceptible. We apply the proposed technique on LGSynth91 and ISCAS85 benchmarks and evaluate its fault tolerance capabilities against errors induced by permanent faults and soft errors. We show that the proposed technique, when it is applied to protect only the 32 most susceptible patterns, achieves on average of all the examined benchmarks, an error coverage improvement of 98% and 94% against errors induced by single stuck-at faults (permanent faults) and soft errors (transient faults), respectively, compared to a reduced TMR scheme that protects the same number of susceptible patterns without ranking them.
fault tolerance, susceptible workload, TMR, output deviations, error detection, permanent & transient faults
Gutierrez Alcala, Mauricio Daniel
29838e60-f993-48e7-8133-0d0ff32129fa
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Kazmierski, Tomasz
a97d7958-40c3-413f-924d-84545216092a
Gutierrez Alcala, Mauricio Daniel
29838e60-f993-48e7-8133-0d0ff32129fa
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Kazmierski, Tomasz
a97d7958-40c3-413f-924d-84545216092a

Gutierrez Alcala, Mauricio Daniel, Tenentes, Vasileios and Kazmierski, Tomasz (2016) Susceptible workload driven selective fault tolerance using a probabilistic fault model. IOLTS'16, Spain. 04 - 06 Jul 2016. 6 pp . (In Press)

Record type: Conference or Workshop Item (Paper)

Abstract

In this paper, we present a novel fault tolerance design technique, which is applicable at the register transfer level, based on protecting the functionality of logic circuits using a probabilistic fault model. The proposed technique selects the most susceptible workload of combinational circuits to protect against probabilistic faults. The workload susceptibility is ranked as the likelihood of any fault to bypass the inherent logical masking of the circuit and propagate an erroneous response to its outputs, when that workload is executed. The workload protection is achieved through a Triple Modular Redundancy (TMR) scheme by using the patterns that have been evaluated as most susceptible. We apply the proposed technique on LGSynth91 and ISCAS85 benchmarks and evaluate its fault tolerance capabilities against errors induced by permanent faults and soft errors. We show that the proposed technique, when it is applied to protect only the 32 most susceptible patterns, achieves on average of all the examined benchmarks, an error coverage improvement of 98% and 94% against errors induced by single stuck-at faults (permanent faults) and soft errors (transient faults), respectively, compared to a reduced TMR scheme that protects the same number of susceptible patterns without ranking them.

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More information

Accepted/In Press date: 5 May 2016
Venue - Dates: IOLTS'16, Spain, 2016-07-04 - 2016-07-06
Keywords: fault tolerance, susceptible workload, TMR, output deviations, error detection, permanent & transient faults
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 395186
URI: https://eprints.soton.ac.uk/id/eprint/395186
PURE UUID: f936d268-94e9-4f2a-959c-7982f916ae99

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Date deposited: 08 Jun 2016 16:12
Last modified: 09 Jan 2018 18:06

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Contributors

Author: Mauricio Daniel Gutierrez Alcala
Author: Vasileios Tenentes
Author: Tomasz Kazmierski

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